drm/mcde/mcde_display.c

93 		u32 val;
106 				val = readl(mcde->regs + MCDE_CRA0);
107 				val &= ~MCDE_CRX0_FLOEN;
108 				writel(val, mcde->regs + MCDE_CRA0);
199 	u32 val;
251 	val = 0 << MCDE_EXTSRCXCONF_BUF_ID_SHIFT;
252 	val |= 1 << MCDE_EXTSRCXCONF_BUF_NB_SHIFT;
253 	val |= 0 << MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT;
257 		val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 <<
261 		val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 <<
263 		val |= MCDE_EXTSRCXCONF_BGR;
266 		val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 <<
270 		val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 <<
272 		val |= MCDE_EXTSRCXCONF_BGR;
275 		val |= MCDE_EXTSRCXCONF_BPP_RGB888 <<
279 		val |= MCDE_EXTSRCXCONF_BPP_RGB888 <<
281 		val |= MCDE_EXTSRCXCONF_BGR;
284 		val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 <<
288 		val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 <<
290 		val |= MCDE_EXTSRCXCONF_BGR;
293 		val |= MCDE_EXTSRCXCONF_BPP_RGB444 <<
297 		val |= MCDE_EXTSRCXCONF_BPP_RGB444 <<
299 		val |= MCDE_EXTSRCXCONF_BGR;
302 		val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 <<
306 		val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 <<
308 		val |= MCDE_EXTSRCXCONF_BGR;
311 		val |= MCDE_EXTSRCXCONF_BPP_RGB565 <<
315 		val |= MCDE_EXTSRCXCONF_BPP_RGB565 <<
317 		val |= MCDE_EXTSRCXCONF_BGR;
320 		val |= MCDE_EXTSRCXCONF_BPP_YCBCR422 <<
328 	writel(val, mcde->regs + conf);
331 	val = MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL;
332 	val |= MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY;
333 	writel(val, mcde->regs + cr);
344 	u32 val;
404 	val = mode->hdisplay << MCDE_OVLXCONF_PPL_SHIFT;
405 	val |= mode->vdisplay << MCDE_OVLXCONF_LPF_SHIFT;
407 	val |= src << MCDE_OVLXCONF_EXTSRC_ID_SHIFT;
408 	writel(val, mcde->regs + conf1);
410 	val = MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA;
411 	val |= 0xff << MCDE_OVLXCONF2_ALPHAVALUE_SHIFT;
429 		val |= MCDE_OVLXCONF2_OPQ;
462 	val |= pixel_fetcher_watermark << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT;
463 	writel(val, mcde->regs + conf2);
471 	val = MCDE_OVLXCR_OVLEN;
472 	val |= MCDE_OVLXCR_COLCCTRL_DISABLED;
473 	val |= MCDE_OVLXCR_BURSTSIZE_8W <<
475 	val |= MCDE_OVLXCR_MAXOUTSTANDING_8_REQ <<
478 	val |= MCDE_OVLXCR_ROTBURSTSIZE_8W <<
480 	writel(val, mcde->regs + cr);
486 	val = ch << MCDE_OVLXCOMP_CH_ID_SHIFT;
487 	writel(val, mcde->regs + comp);
494 	u32 val;
536 		val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE
540 		val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
542 		val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
546 		val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
554 		val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
558 		val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
560 		val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0
565 		val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE
567 		val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER
576 	writel(val, mcde->regs + sync);
579 	val = (mode->hdisplay - 1) << MCDE_CHNLXCONF_PPL_SHIFT;
580 	val |= (mode->vdisplay - 1) << MCDE_CHNLXCONF_LPF_SHIFT;
581 	writel(val, mcde->regs + conf);
587 	val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN |
589 	writel(val, mcde->regs + stat);
614 		val = MCDE_SYNCHCONF_HWREQVEVENT_ACTIVE_VIDEO |
621 			writel(val, mcde->regs + MCDE_SYNCHCONFA);
624 			writel(val, mcde->regs + MCDE_SYNCHCONFB);
634 	u32 val;
651 	val = fifo_wtrmrk << MCDE_CTRLX_FIFOWTRMRK_SHIFT;
663 		val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
664 		val |= MCDE_CTRLX_FORMID_DSI0VID << MCDE_CTRLX_FORMID_SHIFT;
667 		val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
668 		val |= MCDE_CTRLX_FORMID_DSI0CMD << MCDE_CTRLX_FORMID_SHIFT;
671 		val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
672 		val |= MCDE_CTRLX_FORMID_DSI1VID << MCDE_CTRLX_FORMID_SHIFT;
675 		val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
676 		val |= MCDE_CTRLX_FORMID_DSI1CMD << MCDE_CTRLX_FORMID_SHIFT;
679 		val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
680 		val |= MCDE_CTRLX_FORMID_DSI2VID << MCDE_CTRLX_FORMID_SHIFT;
683 		val |= MCDE_CTRLX_FORMTYPE_DSI << MCDE_CTRLX_FORMTYPE_SHIFT;
684 		val |= MCDE_CTRLX_FORMID_DSI2CMD << MCDE_CTRLX_FORMID_SHIFT;
687 		val |= MCDE_CTRLX_FORMTYPE_DPITV << MCDE_CTRLX_FORMTYPE_SHIFT;
688 		val |= MCDE_CTRLX_FORMID_DPIA << MCDE_CTRLX_FORMID_SHIFT;
691 		val |= MCDE_CTRLX_FORMTYPE_DPITV << MCDE_CTRLX_FORMTYPE_SHIFT;
692 		val |= MCDE_CTRLX_FORMID_DPIB << MCDE_CTRLX_FORMID_SHIFT;
695 	writel(val, mcde->regs + ctrl);
698 	val = MCDE_CRX0_BLENDEN |
700 	writel(val, mcde->regs + cr0);
703 	val = readl(mcde->regs + cr1);
726 		val &= ~MCDE_CRX1_CDWIN_MASK;
727 		val &= ~MCDE_CRX1_OUTBPP_MASK;
730 			val |= MCDE_CRX1_CDWIN_24BPP << MCDE_CRX1_CDWIN_SHIFT;
731 			val |= MCDE_CRX1_OUTBPP_24BPP << MCDE_CRX1_OUTBPP_SHIFT;
735 			val |= MCDE_CRX1_CDWIN_24BPP << MCDE_CRX1_CDWIN_SHIFT;
736 			val |= MCDE_CRX1_OUTBPP_24BPP << MCDE_CRX1_OUTBPP_SHIFT;
741 		val &= ~MCDE_CRX1_CLKSEL_MASK;
742 		val |= MCDE_CRX1_CLKSEL_MCDECLK << MCDE_CRX1_CLKSEL_SHIFT;
744 	writel(val, mcde->regs + cr1);
753 	u32 val;
798 	val = MCDE_DSICONF0_CMD8 | MCDE_DSICONF0_DCSVID_NOTGEN;
800 		val |= MCDE_DSICONF0_VID_MODE_VID;
803 		val |= MCDE_DSICONF0_PACKING_RGB888 <<
807 		val |= MCDE_DSICONF0_PACKING_RGB666 <<
813 		val |= MCDE_DSICONF0_PACKING_RGB666 <<
817 		val |= MCDE_DSICONF0_PACKING_RGB565 <<
824 	writel(val, mcde->regs + conf0);
830 	val = MIPI_DCS_WRITE_MEMORY_CONTINUE <<
832 	val |= MIPI_DCS_WRITE_MEMORY_START <<
834 	writel(val, mcde->regs + cmdw);
846 	u32 val;
863 	val = readl(mcde->regs + cr);
864 	val |= MCDE_CRX0_FLOEN;
865 	writel(val, mcde->regs + cr);
874 	u32 val;
891 	val = readl(mcde->regs + cr);
892 	val &= ~MCDE_CRX0_FLOEN;
893 	writel(val, mcde->regs + cr);
918 	u32 val;
946 	val = readl(mcde->regs + ctrl);
947 	if (!(val & MCDE_CTRLX_FIFOEMPTY)) {
979 	u32 val;
1002 	val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT;
1017 	val |= 0 << MCDE_CONF0_OUTMUX0_SHIFT;
1019 	val |= 1 << MCDE_CONF0_OUTMUX1_SHIFT;
1021 	val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT;
1023 	val |= 0 << MCDE_CONF0_OUTMUX3_SHIFT;
1025 	val |= 2 << MCDE_CONF0_OUTMUX4_SHIFT;
1027 	writel(val, mcde->regs + MCDE_CONF0);
1033 	val = (vsw << MCDE_TVBL1_BEL1_SHIFT);
1034 	val |= (vfp << MCDE_TVBL1_BSL1_SHIFT);
1035 	writel(val, mcde->regs + MCDE_TVBL1A);
1037 	writel(val, mcde->regs + MCDE_TVBL2A);
1040 	val = (vbp << MCDE_TVDVO_DVO1_SHIFT);
1042 	val |= (vbp << MCDE_TVDVO_DVO2_SHIFT);
1043 	writel(val, mcde->regs + MCDE_TVDVOA);
1049 	val = ((hsw - 1) << MCDE_TVLBALW_LBW_SHIFT);
1050 	val |= ((hfp - 1) << MCDE_TVLBALW_ALW_SHIFT);
1051 	writel(val, mcde->regs + MCDE_TVLBALWA);
1058 	val = 0;
1060 		val |= MCDE_LCDTIM1B_IHS;
1062 		val |= MCDE_LCDTIM1B_IVS;
1064 		val |= MCDE_LCDTIM1B_IOE;
1066 		val |= MCDE_LCDTIM1B_IPC;
1067 	writel(val, mcde->regs + MCDE_LCDTIM1A);
1081 	u32 val;
1093 	val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT;
1101 	val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT;
1102 	val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT;
1103 	val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT;
1104 	val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT;
1105 	val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT;
1106 	writel(val, mcde->regs + MCDE_CONF0);
1166 	u32 val;
1263 			val = MCDE_VSCRC_VSPOL;
1265 			val = 0;
1266 		writel(val, mcde->regs + MCDE_VSCRC0);
1268 		val = readl(mcde->regs + MCDE_CRC);
1269 		val |= MCDE_CRC_SYCEN0;
1270 		writel(val, mcde->regs + MCDE_CRC);
1293 	val = readl(mcde->regs + MCDE_CR);
1294 	val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN;
1295 	writel(val, mcde->regs + MCDE_CR);
1450 	u32 val;
1453 	val = MCDE_PP_VCMPA |
1459 	writel(val, mcde->regs + MCDE_IMSCPP);