drm/i915/vlv_suspend.c

111 	struct intel_uncore *uncore = &i915->uncore;
118 	s->wr_watermark = intel_uncore_read(uncore, GEN7_WR_WATERMARK);
119 	s->gfx_prio_ctrl = intel_uncore_read(uncore, GEN7_GFX_PRIO_CTRL);
120 	s->arb_mode = intel_uncore_read(uncore, ARB_MODE);
121 	s->gfx_pend_tlb0 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB0);
122 	s->gfx_pend_tlb1 = intel_uncore_read(uncore, GEN7_GFX_PEND_TLB1);
125 		s->lra_limits[i] = intel_uncore_read(uncore, GEN7_LRA_LIMITS(i));
127 	s->media_max_req_count = intel_uncore_read(uncore, GEN7_MEDIA_MAX_REQ_COUNT);
128 	s->gfx_max_req_count = intel_uncore_read(uncore, GEN7_GFX_MAX_REQ_COUNT);
130 	s->render_hwsp = intel_uncore_read(uncore, RENDER_HWS_PGA_GEN7);
131 	s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
132 	s->bsd_hwsp = intel_uncore_read(uncore, BSD_HWS_PGA_GEN7);
133 	s->blt_hwsp = intel_uncore_read(uncore, BLT_HWS_PGA_GEN7);
135 	s->tlb_rd_addr = intel_uncore_read(uncore, GEN7_TLB_RD_ADDR);
138 	s->g3dctl = intel_uncore_read(uncore, VLV_G3DCTL);
139 	s->gsckgctl = intel_uncore_read(uncore, VLV_GSCKGCTL);
140 	s->mbctl = intel_uncore_read(uncore, GEN6_MBCTL);
143 	s->ucgctl1 = intel_uncore_read(uncore, GEN6_UCGCTL1);
144 	s->ucgctl3 = intel_uncore_read(uncore, GEN6_UCGCTL3);
145 	s->rcgctl1 = intel_uncore_read(uncore, GEN6_RCGCTL1);
146 	s->rcgctl2 = intel_uncore_read(uncore, GEN6_RCGCTL2);
147 	s->rstctl = intel_uncore_read(uncore, GEN6_RSTCTL);
148 	s->misccpctl = intel_uncore_read(uncore, GEN7_MISCCPCTL);
151 	s->gfxpause = intel_uncore_read(uncore, GEN6_GFXPAUSE);
152 	s->rpdeuhwtc = intel_uncore_read(uncore, GEN6_RPDEUHWTC);
153 	s->rpdeuc = intel_uncore_read(uncore, GEN6_RPDEUC);
154 	s->ecobus = intel_uncore_read(uncore, ECOBUS);
155 	s->pwrdwnupctl = intel_uncore_read(uncore, VLV_PWRDWNUPCTL);
156 	s->rp_down_timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_TIMEOUT);
157 	s->rp_deucsw = intel_uncore_read(uncore, GEN6_RPDEUCSW);
158 	s->rcubmabdtmr = intel_uncore_read(uncore, GEN6_RCUBMABDTMR);
159 	s->rcedata = intel_uncore_read(uncore, VLV_RCEDATA);
160 	s->spare2gh = intel_uncore_read(uncore, VLV_SPAREG2H);
163 	s->gt_imr = intel_uncore_read(uncore, GTIMR);
164 	s->gt_ier = intel_uncore_read(uncore, GTIER);
165 	s->pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
166 	s->pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
169 		s->gt_scratch[i] = intel_uncore_read(uncore, GEN7_GT_SCRATCH(i));
172 	s->tilectl = intel_uncore_read(uncore, TILECTL);
173 	s->gt_fifoctl = intel_uncore_read(uncore, GTFIFOCTL);
174 	s->gtlc_wake_ctrl = intel_uncore_read(uncore, VLV_GTLC_WAKE_CTRL);
175 	s->gtlc_survive = intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG);
176 	s->pmwgicz = intel_uncore_read(uncore, VLV_PMWGICZ);
179 	s->gu_ctl0 = intel_uncore_read(uncore, VLV_GU_CTL0);
180 	s->gu_ctl1 = intel_uncore_read(uncore, VLV_GU_CTL1);
181 	s->pcbr = intel_uncore_read(uncore, VLV_PCBR);
182 	s->clock_gate_dis2 = intel_uncore_read(uncore, VLV_GUNIT_CLOCK_GATE2);
196 	struct intel_uncore *uncore = &i915->uncore;
203 	intel_uncore_write(uncore, GEN7_WR_WATERMARK, s->wr_watermark);
204 	intel_uncore_write(uncore, GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
205 	intel_uncore_write(uncore, ARB_MODE, s->arb_mode | (0xffff << 16));
206 	intel_uncore_write(uncore, GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
207 	intel_uncore_write(uncore, GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
210 		intel_uncore_write(uncore, GEN7_LRA_LIMITS(i), s->lra_limits[i]);
212 	intel_uncore_write(uncore, GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
213 	intel_uncore_write(uncore, GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
215 	intel_uncore_write(uncore, RENDER_HWS_PGA_GEN7, s->render_hwsp);
216 	intel_uncore_write(uncore, GAM_ECOCHK, s->ecochk);
217 	intel_uncore_write(uncore, BSD_HWS_PGA_GEN7, s->bsd_hwsp);
218 	intel_uncore_write(uncore, BLT_HWS_PGA_GEN7, s->blt_hwsp);
220 	intel_uncore_write(uncore, GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
223 	intel_uncore_write(uncore, VLV_G3DCTL, s->g3dctl);
224 	intel_uncore_write(uncore, VLV_GSCKGCTL, s->gsckgctl);
225 	intel_uncore_write(uncore, GEN6_MBCTL, s->mbctl);
228 	intel_uncore_write(uncore, GEN6_UCGCTL1, s->ucgctl1);
229 	intel_uncore_write(uncore, GEN6_UCGCTL3, s->ucgctl3);
230 	intel_uncore_write(uncore, GEN6_RCGCTL1, s->rcgctl1);
231 	intel_uncore_write(uncore, GEN6_RCGCTL2, s->rcgctl2);
232 	intel_uncore_write(uncore, GEN6_RSTCTL, s->rstctl);
233 	intel_uncore_write(uncore, GEN7_MISCCPCTL, s->misccpctl);
236 	intel_uncore_write(uncore, GEN6_GFXPAUSE, s->gfxpause);
237 	intel_uncore_write(uncore, GEN6_RPDEUHWTC, s->rpdeuhwtc);
238 	intel_uncore_write(uncore, GEN6_RPDEUC, s->rpdeuc);
239 	intel_uncore_write(uncore, ECOBUS, s->ecobus);
240 	intel_uncore_write(uncore, VLV_PWRDWNUPCTL, s->pwrdwnupctl);
241 	intel_uncore_write(uncore, GEN6_RP_DOWN_TIMEOUT, s->rp_down_timeout);
242 	intel_uncore_write(uncore, GEN6_RPDEUCSW, s->rp_deucsw);
243 	intel_uncore_write(uncore, GEN6_RCUBMABDTMR, s->rcubmabdtmr);
244 	intel_uncore_write(uncore, VLV_RCEDATA, s->rcedata);
245 	intel_uncore_write(uncore, VLV_SPAREG2H, s->spare2gh);
248 	intel_uncore_write(uncore, GTIMR, s->gt_imr);
249 	intel_uncore_write(uncore, GTIER, s->gt_ier);
250 	intel_uncore_write(uncore, GEN6_PMIMR, s->pm_imr);
251 	intel_uncore_write(uncore, GEN6_PMIER, s->pm_ier);
254 		intel_uncore_write(uncore, GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
257 	intel_uncore_write(uncore, TILECTL, s->tilectl);
258 	intel_uncore_write(uncore, GTFIFOCTL, s->gt_fifoctl);
264 	intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, ~VLV_GTLC_ALLOWWAKEREQ,
267 	intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, ~VLV_GFX_CLK_FORCE_ON_BIT,
270 	intel_uncore_write(uncore, VLV_PMWGICZ, s->pmwgicz);
273 	intel_uncore_write(uncore, VLV_GU_CTL0, s->gu_ctl0);
274 	intel_uncore_write(uncore, VLV_GU_CTL1, s->gu_ctl1);
275 	intel_uncore_write(uncore, VLV_PCBR, s->pcbr);
276 	intel_uncore_write(uncore, VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
294 			 intel_uncore_read_notrace(&i915->uncore, reg)) & mask)
305 	struct intel_uncore *uncore = &i915->uncore;
308 	intel_uncore_rmw(uncore, VLV_GTLC_SURVIVABILITY_REG, VLV_GFX_CLK_FORCE_ON_BIT,
314 	err = intel_wait_for_register(uncore,
322 			intel_uncore_read(uncore, VLV_GTLC_SURVIVABILITY_REG));
329 	struct intel_uncore *uncore = &i915->uncore;
334 	intel_uncore_rmw(uncore, VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ,
336 	intel_uncore_posting_read(uncore, VLV_GTLC_WAKE_CTRL);
372 	struct intel_uncore *uncore = &i915->uncore;
374 	if (!(intel_uncore_read(uncore, VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
378 	intel_uncore_write(uncore, VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
397 		    (intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask);