i915/soc/intel_dram.c

140 static void chv_detect_mem_freq(struct drm_i915_private *i915)
144 	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
145 	val = vlv_cck_read(i915, CCK_FUSE_REG);
146 	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
150 		i915->mem_freq = 2000;
153 		i915->mem_freq = 1600;
158 static void vlv_detect_mem_freq(struct drm_i915_private *i915)
162 	vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
163 	val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
164 	vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
169 		i915->mem_freq = 800;
172 		i915->mem_freq = 1066;
175 		i915->mem_freq = 1333;
180 static void detect_mem_freq(struct drm_i915_private *i915)
182 	if (IS_PINEVIEW(i915))
183 		pnv_detect_mem_freq(i915);
184 	else if (GRAPHICS_VER(i915) == 5)
185 		ilk_detect_mem_freq(i915);
186 	else if (IS_CHERRYVIEW(i915))
187 		chv_detect_mem_freq(i915);
188 	else if (IS_VALLEYVIEW(i915))
189 		vlv_detect_mem_freq(i915);
191 	if (i915->mem_freq)
192 		drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
274 skl_dram_get_dimm_info(struct drm_i915_private *i915,
278 	if (GRAPHICS_VER(i915) >= 11) {
288 	drm_dbg_kms(&i915->drm,
295 skl_dram_get_channel_info(struct drm_i915_private *i915,
299 	skl_dram_get_dimm_info(i915, &ch->dimm_l,
301 	skl_dram_get_dimm_info(i915, &ch->dimm_s,
305 		drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
319 	drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
335 skl_dram_get_channels_info(struct drm_i915_private *i915)
337 	struct dram_info *dram_info = &i915->dram_info;
342 	val = intel_uncore_read(&i915->uncore,
344 	ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
348 	val = intel_uncore_read(&i915->uncore,
350 	ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
355 		drm_info(&i915->drm, "Number of memory channels is zero\n");
360 		drm_info(&i915->drm, "couldn't get memory rank information\n");
368 	drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
375 skl_get_dram_type(struct drm_i915_private *i915)
379 	val = intel_uncore_read(&i915->uncore,
398 skl_get_dram_info(struct drm_i915_private *i915)
400 	struct dram_info *dram_info = &i915->dram_info;
403 	dram_info->type = skl_get_dram_type(i915);
404 	drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
407 	ret = skl_dram_get_channels_info(i915);
492 static int bxt_get_dram_info(struct drm_i915_private *i915)
494 	struct dram_info *dram_info = &i915->dram_info;
506 		val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
515 		drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
519 		drm_dbg_kms(&i915->drm,
533 		drm_info(&i915->drm, "couldn't get memory information\n");
602 static int gen11_get_dram_info(struct drm_i915_private *i915)
604 	int ret = skl_get_dram_info(i915);
609 	return icl_pcode_read_mem_global_info(i915);
612 static int gen12_get_dram_info(struct drm_i915_private *i915)
614 	i915->dram_info.wm_lv_0_adjust_needed = false;
616 	return icl_pcode_read_mem_global_info(i915);
619 static int xelpdp_get_dram_info(struct drm_i915_private *i915)
621 	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
622 	struct dram_info *dram_info = &i915->dram_info;
655 void intel_dram_detect(struct drm_i915_private *i915)
657 	struct dram_info *dram_info = &i915->dram_info;
660 	detect_mem_freq(i915);
662 	if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
669 	dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
671 	if (DISPLAY_VER(i915) >= 14)
672 		ret = xelpdp_get_dram_info(i915);
673 	else if (GRAPHICS_VER(i915) >= 12)
674 		ret = gen12_get_dram_info(i915);
675 	else if (GRAPHICS_VER(i915) >= 11)
676 		ret = gen11_get_dram_info(i915);
677 	else if (IS_GEN9_LP(i915))
678 		ret = bxt_get_dram_info(i915);
680 		ret = skl_get_dram_info(i915);
684 	drm_dbg_kms(&i915->drm, "Num qgv points %u\n", dram_info->num_qgv_points);
686 	drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
688 	drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
692 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
702 void intel_dram_edram_detect(struct drm_i915_private *i915)
706 	if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
709 	edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
720 	if (GRAPHICS_VER(i915) < 9)
721 		i915->edram_size_mb = 128;
723 		i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
725 	drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);