Lines Matching defs:spin

14 int igt_spinner_init(struct igt_spinner *spin, struct intel_gt *gt)
18 memset(spin, 0, sizeof(*spin));
19 spin->gt = gt;
21 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
22 if (IS_ERR(spin->hws)) {
23 err = PTR_ERR(spin->hws);
26 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC);
28 spin->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
29 if (IS_ERR(spin->obj)) {
30 err = PTR_ERR(spin->obj);
37 i915_gem_object_put(spin->hws);
79 int igt_spinner_pin(struct igt_spinner *spin,
85 if (spin->ce && WARN_ON(spin->ce != ce))
87 spin->ce = ce;
89 if (!spin->seqno) {
90 vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB, &spin->hws_vma);
94 spin->seqno = memset(vaddr, 0xff, PAGE_SIZE);
97 if (!spin->batch) {
100 mode = intel_gt_coherent_map_type(spin->gt, spin->obj, false);
101 vaddr = igt_spinner_pin_obj(ce, ww, spin->obj, mode, &spin->batch_vma);
105 spin->batch = vaddr;
123 igt_spinner_create_request(struct igt_spinner *spin,
134 GEM_BUG_ON(spin->gt != ce->vm->gt);
139 if (!spin->batch) {
140 err = igt_spinner_pin(spin, ce, NULL);
145 hws = spin->hws_vma;
146 vma = spin->batch_vma;
160 batch = spin->batch;
220 hws_seqno(const struct igt_spinner *spin, const struct i915_request *rq)
222 u32 *seqno = spin->seqno + seqno_offset(rq->fence.context);
227 void igt_spinner_end(struct igt_spinner *spin)
229 if (!spin->batch)
232 *spin->batch = MI_BATCH_BUFFER_END;
233 intel_gt_chipset_flush(spin->gt);
236 void igt_spinner_fini(struct igt_spinner *spin)
238 igt_spinner_end(spin);
240 if (spin->batch) {
241 i915_vma_unpin(spin->batch_vma);
242 i915_gem_object_unpin_map(spin->obj);
244 i915_gem_object_put(spin->obj);
246 if (spin->seqno) {
247 i915_vma_unpin(spin->hws_vma);
248 i915_gem_object_unpin_map(spin->hws);
250 i915_gem_object_put(spin->hws);
253 bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq)
258 return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq),
261 wait_for(i915_seqno_passed(hws_seqno(spin, rq),