i915/selftests/i915_perf.c

161 static int write_timestamp(struct i915_request *rq, int slot)
166 	cs = intel_ring_begin(rq, 6);
171 	if (GRAPHICS_VER(rq->i915) >= 8)
183 	intel_ring_advance(rq, cs);
188 static ktime_t poll_status(struct i915_request *rq, int slot)
190 	while (!intel_read_status_page(rq->engine, slot) &&
191 	       !i915_request_completed(rq))
201 	struct i915_request *rq;
224 	rq = intel_engine_create_kernel_request(stream->engine);
225 	if (IS_ERR(rq)) {
226 		err = PTR_ERR(rq);
230 	if (rq->engine->emit_init_breadcrumb) {
231 		err = rq->engine->emit_init_breadcrumb(rq);
233 			i915_request_add(rq);
238 	err = write_timestamp(rq, 0x100);
240 		i915_request_add(rq);
244 	err = rq->engine->emit_bb_start(rq,
248 		i915_request_add(rq);
252 	err = write_timestamp(rq, 0x102);
254 		i915_request_add(rq);
258 	i915_request_get(rq);
259 	i915_request_add(rq);
262 	t0 = poll_status(rq, 0x100);
263 	t1 = poll_status(rq, 0x102);
283 	i915_request_put(rq);
294 	struct i915_request *rq;
319 	rq = intel_context_create_request(ce);
320 	if (IS_ERR(rq)) {
321 		err = PTR_ERR(rq);
324 	i915_request_get(rq);
326 	if (rq->engine->emit_init_breadcrumb) {
327 		err = rq->engine->emit_init_breadcrumb(rq);
329 			i915_request_add(rq);
335 	cs = intel_ring_begin(rq, 2 * 32 + 2);
338 		i915_request_add(rq);
348 	intel_ring_advance(rq, cs);
351 	err = rq->engine->emit_bb_start(rq,
355 		i915_request_add(rq);
360 	store = memset32(rq->engine->status_page.addr + 512, 0, 32);
364 		cs = intel_ring_begin(rq, 4);
367 			i915_request_add(rq);
378 		*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +
382 		intel_ring_advance(rq, cs);
385 	i915_request_add(rq);
387 	if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, HZ / 2) < 0) {
412 	i915_request_put(rq);