drm/i915/intel_device_info.c

216 static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
218 	const struct intel_device_info *info = INTEL_INFO(i915);
219 	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
222 	u16 devid = INTEL_DEVID(i915);
226 	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
235 		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
267 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
270 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
272 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
279 	if (drm_WARN_ON(&i915->drm, !addr))
291 		drm_dbg(&i915->drm,
306 static void intel_ipver_early_init(struct drm_i915_private *i915)
308 	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
310 	if (!HAS_GMD_ID(i915)) {
311 		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
316 		RUNTIME_INFO(i915)->media.ip =
317 			RUNTIME_INFO(i915)->graphics.ip;
321 	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
325 	    INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
326 		RUNTIME_INFO(i915)->graphics.ip.ver = 12;
327 		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
329 	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
335  * @i915: the i915 device
340 void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
342 	intel_ipver_early_init(i915);
343 	intel_device_info_subplatform_init(i915);
348  * @dev_priv: the i915 device
382  * Note: i915 is only an allocated blob of memory at this point.
384 void intel_device_info_driver_create(struct drm_i915_private *i915,
391 	i915->__info = match_info;
394 	runtime = RUNTIME_INFO(i915);
395 	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));