drm/i915/i915_pmu.c

154 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
174 	if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS)
185 	struct drm_i915_private *i915 = gt->i915;
190 	if (HAS_RC6p(i915))
193 	if (HAS_RC6pp(i915))
223 	struct drm_i915_private *i915 = gt->i915;
225 	struct i915_pmu *pmu = &i915->pmu;
264 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
268 	for_each_gt(gt, i915, i) {
284 	struct i915_pmu *pmu = &gt->i915->pmu;
303 	struct i915_pmu *pmu = &gt->i915->pmu;
325 	struct i915_pmu *pmu = &gt->i915->pmu;
349 static bool exclusive_mmio_access(const struct drm_i915_private *i915)
356 	return GRAPHICS_VER(i915) == 7;
397 	struct drm_i915_private *i915 = gt->i915;
402 	if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
415 		if (exclusive_mmio_access(i915)) {
438 	struct drm_i915_private *i915 = gt->i915;
440 	struct i915_pmu *pmu = &i915->pmu;
484 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
504 	for_each_gt(gt, i915, i) {
520 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
522 	drm_WARN_ON(&i915->drm, event->parent);
524 	drm_dev_put(&i915->drm);
536 		if (GRAPHICS_VER(engine->i915) < 6)
547 config_status(struct drm_i915_private *i915, u64 config)
549 	struct intel_gt *gt = to_gt(i915);
552 	unsigned int max_gt_id = HAS_EXTRA_GT_LIST(i915) ? 1 : 0;
559 		if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
564 		if (GRAPHICS_VER(i915) < 6)
587 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
590 	engine = intel_engine_lookup_user(i915, engine_event_class(event),
601 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
627 		ret = config_status(i915, event->attr.config);
632 		drm_dev_get(&i915->drm);
642 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
649 		engine = intel_engine_lookup_user(i915,
653 		if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {
685 			val = get_rc6(i915->gt[gt_id]);
688 			val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
718 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
751 		engine = intel_engine_lookup_user(i915,
781 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
794 		engine = intel_engine_lookup_user(i915,
837 	struct drm_i915_private *i915 =
838 		container_of(event->pmu, typeof(*i915), pmu.base);
839 	struct i915_pmu *pmu = &i915->pmu;
986 	struct drm_i915_private *i915 = pmu_to_i915(pmu);
1016 	for_each_gt(gt, i915, j) {
1020 			if (!config_status(i915, config))
1025 	for_each_uabi_engine(engine, i915) {
1052 	for_each_gt(gt, i915, j) {
1057 			if (config_status(i915, config))
1060 			if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
1072 				if (events[i].global || !HAS_EXTRA_GT_LIST(i915))
1089 	for_each_uabi_engine(engine, i915) {
1204 				      "perf/x86/intel/i915:online",
1208 		pr_notice("Failed to setup cpuhp state for i915 PMU! (%d)\n",
1235 static bool is_igp(struct drm_i915_private *i915)
1237 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1246 void i915_pmu_register(struct drm_i915_private *i915)
1248 	struct i915_pmu *pmu = &i915->pmu;
1258 	if (GRAPHICS_VER(i915) <= 2) {
1259 		drm_info(&i915->drm, "PMU not supported for this GPU.");
1269 	if (!is_igp(i915)) {
1272 				      dev_name(i915->drm.dev));
1278 		pmu->name = "i915";
1321 	if (!is_igp(i915))
1324 	drm_notice(&i915->drm, "Failed to register PMU!\n");
1327 void i915_pmu_unregister(struct drm_i915_private *i915)
1329 	struct i915_pmu *pmu = &i915->pmu;
1349 	if (!is_igp(i915))