drm/i915/i915_irq.c

82 		    i915_reg_t iir, i915_reg_t ier)
90 	intel_uncore_write(uncore, iir, 0xffffffff);
91 	intel_uncore_posting_read(uncore, iir);
92 	intel_uncore_write(uncore, iir, 0xffffffff);
93 	intel_uncore_posting_read(uncore, iir);
148 		   i915_reg_t iir)
150 	gen3_assert_iir_is_zero(uncore, iir);
263 		u32 iir, gt_iir, pm_iir;
270 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
272 		if (gt_iir == 0 && pm_iir == 0 && iir == 0)
298 		if (iir & I915_DISPLAY_PORT_INTERRUPT)
302 		 * signalled in iir */
303 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
305 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
313 		if (iir)
314 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
349 		u32 master_ctl, iir;
355 		iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
357 		if (master_ctl == 0 && iir == 0)
380 		if (iir & I915_DISPLAY_PORT_INTERRUPT)
384 		 * signalled in iir */
385 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
387 		if (iir & (I915_LPE_PIPE_A_INTERRUPT |
396 		if (iir)
397 			intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
436 	/* disable master interrupt before clearing iir  */
1004 		u16 iir;
1006 		iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
1007 		if (iir == 0)
1013 		 * signalled in iir */
1014 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1016 		if (iir & I915_MASTER_ERROR_INTERRUPT)
1019 		intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
1021 		if (iir & I915_USER_INTERRUPT)
1022 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
1024 		if (iir & I915_MASTER_ERROR_INTERRUPT)
1027 		i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1107 		u32 iir;
1109 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1110 		if (iir == 0)
1116 		    iir & I915_DISPLAY_PORT_INTERRUPT)
1120 		 * signalled in iir */
1121 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1123 		if (iir & I915_MASTER_ERROR_INTERRUPT)
1126 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1128 		if (iir & I915_USER_INTERRUPT)
1129 			intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
1131 		if (iir & I915_MASTER_ERROR_INTERRUPT)
1137 		i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1233 		u32 iir;
1235 		iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1236 		if (iir == 0)
1241 		if (iir & I915_DISPLAY_PORT_INTERRUPT)
1245 		 * signalled in iir */
1246 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1248 		if (iir & I915_MASTER_ERROR_INTERRUPT)
1251 		intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1253 		if (iir & I915_USER_INTERRUPT)
1255 					    iir);
1257 		if (iir & I915_BSD_USER_INTERRUPT)
1259 					    iir >> 25);
1261 		if (iir & I915_MASTER_ERROR_INTERRUPT)
1267 		i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);