Lines Matching refs:dev_priv
178 struct drm_i915_private *dev_priv =
179 container_of(work, typeof(*dev_priv), l3_parity.error_work);
180 struct intel_gt *gt = to_gt(dev_priv);
190 mutex_lock(&dev_priv->drm.struct_mutex);
193 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
196 misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
198 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);
200 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
204 if (drm_WARN_ON_ONCE(&dev_priv->drm,
205 slice >= NUM_L3_SLICES(dev_priv)))
208 dev_priv->l3_parity.which_slice &= ~(1<<slice);
212 error_status = intel_uncore_read(&dev_priv->uncore, reg);
217 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
218 intel_uncore_posting_read(&dev_priv->uncore, reg);
227 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
230 drm_dbg(&dev_priv->drm,
240 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
243 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
245 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
248 mutex_unlock(&dev_priv->drm.struct_mutex);
253 struct drm_i915_private *dev_priv = arg;
256 if (!intel_irqs_enabled(dev_priv))
260 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
268 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR);
269 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
270 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
290 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
291 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);
294 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir);
296 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir);
299 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
303 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
307 intel_lpe_audio_irq_handler(dev_priv);
314 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
316 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
317 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
320 gen6_gt_irq_handler(to_gt(dev_priv), gt_iir);
322 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir);
325 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
327 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
330 pmu_irq_stats(dev_priv, ret);
332 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
339 struct drm_i915_private *dev_priv = arg;
342 if (!intel_irqs_enabled(dev_priv))
346 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
354 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
355 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
375 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
376 ier = intel_uncore_rmw(&dev_priv->uncore, VLV_IER, ~0, 0);
378 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
381 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
385 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
390 intel_lpe_audio_irq_handler(dev_priv);
397 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
399 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier);
400 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
403 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
405 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
408 pmu_irq_stats(dev_priv, ret);
410 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
513 struct drm_i915_private *dev_priv = arg;
514 void __iomem * const regs = intel_uncore_regs(&dev_priv->uncore);
517 if (!intel_irqs_enabled(dev_priv))
527 gen8_gt_irq_handler(to_gt(dev_priv), master_ctl);
531 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
532 gen8_de_irq_handler(dev_priv, master_ctl);
533 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
538 pmu_irq_stats(dev_priv, IRQ_HANDLED);
662 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
664 struct intel_uncore *uncore = &dev_priv->uncore;
666 if (HAS_PCH_NOP(dev_priv))
671 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
672 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff);
677 static void ilk_irq_reset(struct drm_i915_private *dev_priv)
679 struct intel_uncore *uncore = &dev_priv->uncore;
682 dev_priv->irq_mask = ~0u;
684 if (GRAPHICS_VER(dev_priv) == 7)
687 if (IS_HASWELL(dev_priv)) {
692 gen5_gt_irq_reset(to_gt(dev_priv));
694 ibx_irq_reset(dev_priv);
697 static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
699 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0);
700 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
702 gen5_gt_irq_reset(to_gt(dev_priv));
704 spin_lock_irq(&dev_priv->irq_lock);
705 if (dev_priv->display.irq.display_irqs_enabled)
706 vlv_display_irq_reset(dev_priv);
707 spin_unlock_irq(&dev_priv->irq_lock);
710 static void gen8_irq_reset(struct drm_i915_private *dev_priv)
712 struct intel_uncore *uncore = &dev_priv->uncore;
716 gen8_gt_irq_reset(to_gt(dev_priv));
717 gen8_display_irq_reset(dev_priv);
720 if (HAS_PCH_SPLIT(dev_priv))
721 ibx_irq_reset(dev_priv);
725 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
727 struct intel_gt *gt = to_gt(dev_priv);
730 gen11_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
733 gen11_display_irq_reset(dev_priv);
739 static void dg1_irq_reset(struct drm_i915_private *dev_priv)
741 struct intel_uncore *uncore = &dev_priv->uncore;
745 dg1_master_intr_disable(intel_uncore_regs(&dev_priv->uncore));
747 for_each_gt(gt, dev_priv, i)
750 gen11_display_irq_reset(dev_priv);
758 static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
760 struct intel_uncore *uncore = &dev_priv->uncore;
763 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
765 gen8_gt_irq_reset(to_gt(dev_priv));
769 spin_lock_irq(&dev_priv->irq_lock);
770 if (dev_priv->display.irq.display_irqs_enabled)
771 vlv_display_irq_reset(dev_priv);
772 spin_unlock_irq(&dev_priv->irq_lock);
775 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
777 gen5_gt_irq_postinstall(to_gt(dev_priv));
779 ilk_de_irq_postinstall(dev_priv);
782 static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
784 gen5_gt_irq_postinstall(to_gt(dev_priv));
786 spin_lock_irq(&dev_priv->irq_lock);
787 if (dev_priv->display.irq.display_irqs_enabled)
788 vlv_display_irq_postinstall(dev_priv);
789 spin_unlock_irq(&dev_priv->irq_lock);
791 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
792 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);
795 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
797 gen8_gt_irq_postinstall(to_gt(dev_priv));
798 gen8_de_irq_postinstall(dev_priv);
800 gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore));
803 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
805 struct intel_gt *gt = to_gt(dev_priv);
810 gen11_de_irq_postinstall(dev_priv);
815 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);
818 static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
820 struct intel_uncore *uncore = &dev_priv->uncore;
825 for_each_gt(gt, dev_priv, i)
830 dg1_de_irq_postinstall(dev_priv);
836 static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
838 gen8_gt_irq_postinstall(to_gt(dev_priv));
840 spin_lock_irq(&dev_priv->irq_lock);
841 if (dev_priv->display.irq.display_irqs_enabled)
842 vlv_display_irq_postinstall(dev_priv);
843 spin_unlock_irq(&dev_priv->irq_lock);
845 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
846 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
849 static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
851 struct intel_uncore *uncore = &dev_priv->uncore;
853 i9xx_pipestat_irq_reset(dev_priv);
856 dev_priv->irq_mask = ~0u;
880 static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
882 struct intel_uncore *uncore = &dev_priv->uncore;
885 intel_uncore_write16(uncore, EMR, i9xx_error_mask(dev_priv));
888 dev_priv->irq_mask =
899 gen2_irq_init(uncore, dev_priv->irq_mask, enable_mask);
903 spin_lock_irq(&dev_priv->irq_lock);
904 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
905 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
906 spin_unlock_irq(&dev_priv->irq_lock);
937 static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
940 drm_dbg(&dev_priv->drm, "Master Error: EIR 0x%04x\n", eir);
943 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
946 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
947 intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
950 static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
955 *eir = intel_uncore_read(&dev_priv->uncore, EIR);
956 intel_uncore_write(&dev_priv->uncore, EIR, *eir);
958 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
972 emr = intel_uncore_read(&dev_priv->uncore, EMR);
973 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff);
974 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck);
977 static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
980 drm_dbg(&dev_priv->drm, "Master Error, EIR 0x%08x\n", eir);
983 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
986 drm_dbg(&dev_priv->drm, "PGTBL_ER: 0x%08x\n",
987 intel_uncore_read(&dev_priv->uncore, PGTBL_ER));
992 struct drm_i915_private *dev_priv = arg;
995 if (!intel_irqs_enabled(dev_priv))
999 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1006 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
1014 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1017 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
1019 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
1022 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
1025 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
1027 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1030 pmu_irq_stats(dev_priv, ret);
1032 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1037 static void i915_irq_reset(struct drm_i915_private *dev_priv)
1039 struct intel_uncore *uncore = &dev_priv->uncore;
1041 if (I915_HAS_HOTPLUG(dev_priv)) {
1042 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
1043 intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_STAT, 0, 0);
1046 i9xx_pipestat_irq_reset(dev_priv);
1049 dev_priv->irq_mask = ~0u;
1052 static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
1054 struct intel_uncore *uncore = &dev_priv->uncore;
1057 intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv));
1060 dev_priv->irq_mask =
1073 if (I915_HAS_HOTPLUG(dev_priv)) {
1077 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
1080 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
1084 spin_lock_irq(&dev_priv->irq_lock);
1085 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
1086 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
1087 spin_unlock_irq(&dev_priv->irq_lock);
1089 i915_enable_asle_pipestat(dev_priv);
1094 struct drm_i915_private *dev_priv = arg;
1097 if (!intel_irqs_enabled(dev_priv))
1101 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1109 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1115 if (I915_HAS_HOTPLUG(dev_priv) &&
1117 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1121 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1124 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
1126 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1129 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
1132 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
1135 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1137 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1140 pmu_irq_stats(dev_priv, ret);
1142 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1147 static void i965_irq_reset(struct drm_i915_private *dev_priv)
1149 struct intel_uncore *uncore = &dev_priv->uncore;
1151 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
1154 i9xx_pipestat_irq_reset(dev_priv);
1157 dev_priv->irq_mask = ~0u;
1179 static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
1181 struct intel_uncore *uncore = &dev_priv->uncore;
1184 intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv));
1187 dev_priv->irq_mask =
1202 if (IS_G4X(dev_priv))
1205 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
1209 spin_lock_irq(&dev_priv->irq_lock);
1210 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
1211 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
1212 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
1213 spin_unlock_irq(&dev_priv->irq_lock);
1215 i915_enable_asle_pipestat(dev_priv);
1220 struct drm_i915_private *dev_priv = arg;
1223 if (!intel_irqs_enabled(dev_priv))
1227 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1235 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1242 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1246 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1249 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
1251 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1254 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0],
1258 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0],
1262 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
1265 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1267 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1270 pmu_irq_stats(dev_priv, IRQ_HANDLED);
1272 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1279 * @dev_priv: i915 device instance
1284 void intel_irq_init(struct drm_i915_private *dev_priv)
1288 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
1290 dev_priv->l3_parity.remap_info[i] = NULL;
1293 if (HAS_GT_UC(dev_priv) && GRAPHICS_VER(dev_priv) < 11)
1294 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16;
1311 static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
1313 if (HAS_GMCH(dev_priv)) {
1314 if (IS_CHERRYVIEW(dev_priv))
1316 else if (IS_VALLEYVIEW(dev_priv))
1318 else if (GRAPHICS_VER(dev_priv) == 4)
1320 else if (GRAPHICS_VER(dev_priv) == 3)
1325 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
1327 else if (GRAPHICS_VER(dev_priv) >= 11)
1329 else if (GRAPHICS_VER(dev_priv) >= 8)
1336 static void intel_irq_reset(struct drm_i915_private *dev_priv)
1338 if (HAS_GMCH(dev_priv)) {
1339 if (IS_CHERRYVIEW(dev_priv))
1340 cherryview_irq_reset(dev_priv);
1341 else if (IS_VALLEYVIEW(dev_priv))
1342 valleyview_irq_reset(dev_priv);
1343 else if (GRAPHICS_VER(dev_priv) == 4)
1344 i965_irq_reset(dev_priv);
1345 else if (GRAPHICS_VER(dev_priv) == 3)
1346 i915_irq_reset(dev_priv);
1348 i8xx_irq_reset(dev_priv);
1350 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
1351 dg1_irq_reset(dev_priv);
1352 else if (GRAPHICS_VER(dev_priv) >= 11)
1353 gen11_irq_reset(dev_priv);
1354 else if (GRAPHICS_VER(dev_priv) >= 8)
1355 gen8_irq_reset(dev_priv);
1357 ilk_irq_reset(dev_priv);
1361 static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
1363 if (HAS_GMCH(dev_priv)) {
1364 if (IS_CHERRYVIEW(dev_priv))
1365 cherryview_irq_postinstall(dev_priv);
1366 else if (IS_VALLEYVIEW(dev_priv))
1367 valleyview_irq_postinstall(dev_priv);
1368 else if (GRAPHICS_VER(dev_priv) == 4)
1369 i965_irq_postinstall(dev_priv);
1370 else if (GRAPHICS_VER(dev_priv) == 3)
1371 i915_irq_postinstall(dev_priv);
1373 i8xx_irq_postinstall(dev_priv);
1375 if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10))
1376 dg1_irq_postinstall(dev_priv);
1377 else if (GRAPHICS_VER(dev_priv) >= 11)
1378 gen11_irq_postinstall(dev_priv);
1379 else if (GRAPHICS_VER(dev_priv) >= 8)
1380 gen8_irq_postinstall(dev_priv);
1382 ilk_irq_postinstall(dev_priv);
1388 * @dev_priv: i915 device instance
1397 int intel_irq_install(struct drm_i915_private *dev_priv)
1399 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
1407 dev_priv->runtime_pm.irqs_enabled = true;
1409 dev_priv->irq_enabled = true;
1411 intel_irq_reset(dev_priv);
1413 ret = request_irq(irq, intel_irq_handler(dev_priv),
1414 IRQF_SHARED, DRIVER_NAME, dev_priv);
1416 dev_priv->irq_enabled = false;
1420 intel_irq_postinstall(dev_priv);
1427 * @dev_priv: i915 device instance
1432 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
1434 int irq = to_pci_dev(dev_priv->drm.dev)->irq;
1442 if (!dev_priv->irq_enabled)
1445 dev_priv->irq_enabled = false;
1447 intel_irq_reset(dev_priv);
1449 free_irq(irq, dev_priv);
1451 intel_hpd_cancel_work(dev_priv);
1452 dev_priv->runtime_pm.irqs_enabled = false;
1457 * @dev_priv: i915 device instance
1462 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
1464 intel_irq_reset(dev_priv);
1465 dev_priv->runtime_pm.irqs_enabled = false;
1466 intel_synchronize_irq(dev_priv);
1471 * @dev_priv: i915 device instance
1476 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
1478 dev_priv->runtime_pm.irqs_enabled = true;
1479 intel_irq_reset(dev_priv);
1480 intel_irq_postinstall(dev_priv);
1483 bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1485 return dev_priv->runtime_pm.irqs_enabled;