Lines Matching defs:gt
47 #include "gt/intel_engine_regs.h"
48 #include "gt/intel_gt.h"
49 #include "gt/intel_gt_mcr.h"
50 #include "gt/intel_gt_pm.h"
51 #include "gt/intel_gt_regs.h"
52 #include "gt/uc/intel_guc_capture.h"
458 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
463 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
472 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
724 struct intel_gt_coredump *gt)
728 intel_gt_info_print(>->info, &p);
729 intel_sseu_print_topology(gt->_gt->i915, >->info.sseu, &p);
733 struct intel_gt_coredump *gt)
735 err_printf(m, "IER: 0x%08x\n", gt->ier);
736 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
740 struct intel_gt_coredump *gt)
744 err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
746 gt->clock_frequency, gt->clock_period_ns);
747 err_printf(m, "EIR: 0x%08x\n", gt->eir);
748 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
750 for (i = 0; i < gt->ngtier; i++)
751 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
755 struct intel_gt_coredump *gt)
757 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
760 err_printf(m, "ERROR: 0x%08x\n", gt->error);
761 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
766 gt->fault_data1, gt->fault_data0);
769 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
772 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
775 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
786 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
787 !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
791 gt->sfc_done[i]);
794 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done);
799 struct intel_gt_coredump *gt)
803 for (i = 0; i < gt->nfence; i++)
804 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]);
808 struct intel_gt_coredump *gt)
812 for (ee = gt->engine; ee; ee = ee->next) {
815 if (gt->uc && gt->uc->guc.is_guc_capture) {
859 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
880 if (error->gt) {
883 if (error->gt->uc && error->gt->uc->guc.is_guc_capture)
886 err_print_gt_display(m, error->gt);
887 err_print_gt_global_nonguc(m, error->gt);
888 err_print_gt_fences(m, error->gt);
895 err_print_gt_global(m, error->gt);
897 err_print_gt_engines(m, error->gt);
899 if (error->gt->uc)
900 err_print_uc(m, error->gt->uc);
902 err_print_gt_info(m, error->gt);
1047 static void cleanup_gt(struct intel_gt_coredump *gt)
1049 while (gt->engine) {
1050 struct intel_engine_coredump *ee = gt->engine;
1052 gt->engine = ee->next;
1059 if (gt->uc)
1060 cleanup_uc(gt->uc);
1062 kfree(gt);
1070 while (error->gt) {
1071 struct intel_gt_coredump *gt = error->gt;
1073 error->gt = gt->next;
1074 cleanup_gt(gt);
1086 i915_vma_coredump_create(const struct intel_gt *gt,
1092 struct i915_ggtt *ggtt = gt->ggtt;
1130 i915_gem_get_pat_index(gt->i915,
1135 i915_gem_get_pat_index(gt->i915,
1208 static void gt_record_fences(struct intel_gt_coredump *gt)
1210 struct i915_ggtt *ggtt = gt->_gt->ggtt;
1211 struct intel_uncore *uncore = gt->_gt->uncore;
1216 gt->fence[i] =
1221 gt->fence[i] =
1226 gt->fence[i] =
1229 gt->nfence = i;
1245 if (MEDIA_VER(i915) >= 13 && engine->gt->type == GT_MEDIA)
1250 ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
1513 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma,
1526 ret = i915_vma_coredump_create(gt, vma_res, compress, name);
1534 const struct intel_gt *gt,
1539 add_vma(ee, create_vma_coredump(gt, vma, name, compress));
1621 i915_vma_coredump_create(engine->gt, vma_res,
1631 add_vma_coredump(ee, engine->gt, engine->status_page.vma,
1634 add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,
1654 drm_info(&engine->gt->i915->drm, "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n",
1668 intel_guc_capture_get_matching_node(engine->gt, ee, ce);
1678 gt_record_engines(struct intel_gt_coredump *gt,
1686 for_each_engine(engine, gt->_gt, id) {
1698 gt->simulated |= ee->simulated;
1706 ee->next = gt->engine;
1707 gt->engine = ee;
1729 gt_record_uc(struct intel_gt_coredump *gt,
1732 const struct intel_uc *uc = >->_gt->uc;
1750 * gt->clock_frequency fields saved elsewhere).
1752 error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP);
1753 error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
1755 error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,
1767 static void gt_record_display_regs(struct intel_gt_coredump *gt)
1769 struct intel_uncore *uncore = gt->_gt->uncore;
1773 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1776 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1778 gt->ier = intel_uncore_read(uncore, VLV_IER);
1780 gt->ier = intel_uncore_read(uncore, DEIER);
1782 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1784 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1788 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt)
1790 struct intel_uncore *uncore = gt->_gt->uncore;
1795 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1796 gt->ngtier = 1;
1798 gt->gtier[0] =
1801 gt->gtier[1] =
1803 gt->gtier[2] =
1805 gt->gtier[3] =
1808 gt->gtier[4] =
1811 gt->gtier[5] =
1814 gt->ngtier = 6;
1817 gt->gtier[i] =
1819 gt->ngtier = 4;
1821 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1822 gt->ngtier = 1;
1825 gt->eir = intel_uncore_read(uncore, EIR);
1826 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1833 static void gt_record_global_regs(struct intel_gt_coredump *gt)
1835 struct intel_uncore *uncore = gt->_gt->uncore;
1850 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1853 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1856 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
1858 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
1861 gt->fault_data0 = intel_uncore_read(uncore,
1863 gt->fault_data1 = intel_uncore_read(uncore,
1866 gt->fault_data0 = intel_uncore_read(uncore,
1868 gt->fault_data1 = intel_uncore_read(uncore,
1873 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1874 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1875 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1880 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1884 gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1885 gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1891 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1892 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1896 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1899 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1908 if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
1909 !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1912 gt->sfc_done[i] =
1916 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1920 static void gt_record_info(struct intel_gt_coredump *gt)
1922 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info));
1923 gt->clock_frequency = gt->_gt->clock_frequency;
1924 gt->clock_period_ns = gt->_gt->clock_period_ns;
1952 struct intel_gt_coredump *gt;
1955 for (gt = error->gt; gt; gt = gt->next) {
1958 for (cs = gt->engine; cs; cs = cs->next) {
2036 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
2044 gc->_gt = gt;
2045 gc->awake = intel_gt_pm_is_awake(gt);
2068 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
2084 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
2095 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2097 struct drm_i915_private *i915 = gt->i915;
2109 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags);
2110 if (error->gt) {
2113 compress = i915_vma_capture_prepare(error->gt);
2115 kfree(error->gt);
2121 error->gt->uc = gt_record_uc(error->gt, compress);
2122 if (error->gt->uc) {
2124 error->gt->uc->guc.is_guc_capture = true;
2126 GEM_BUG_ON(error->gt->uc->guc.is_guc_capture);
2130 gt_record_info(error->gt);
2131 gt_record_engines(error->gt, engine_mask, compress, dump_flags);
2134 i915_vma_capture_finish(error->gt, compress);
2136 error->simulated |= error->gt->simulated;
2145 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2154 dump = __i915_gpu_coredump(gt, engine_mask, dump_flags);
2191 * @gt: intel_gt which originated the hang
2200 void i915_capture_error_state(struct intel_gt *gt,
2205 error = i915_gpu_coredump(gt, engine_mask, dump_flags);
2207 cmpxchg(>->i915->gpu_error.first_error, NULL, error);
2252 void intel_klog_error_capture(struct intel_gt *gt,
2256 struct drm_i915_private *i915 = gt->i915;
2266 if (test_bit(I915_RESET_BACKOFF, >->reset.flags)) {
2267 drm_err(>->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n",
2280 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);