drm/i915/i915_getparam.c

22 	int value = 0;
32 		value = pdev->device;
35 		value = pdev->revision;
38 		value = to_gt(i915)->ggtt->num_fences;
41 		value = !!i915->display.overlay;
44 		value = !!intel_engine_lookup_user(i915,
48 		value = !!intel_engine_lookup_user(i915,
52 		value = !!intel_engine_lookup_user(i915,
56 		value = !!intel_engine_lookup_user(i915,
60 		value = HAS_LLC(i915);
63 		value = HAS_WT(i915);
66 		value = INTEL_PPGTT(i915);
69 		value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
72 		value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
75 		value = i915_cmd_parser_get_version(i915);
78 		value = intel_sseu_subslice_total(sseu);
79 		if (!value)
83 		value = sseu->eu_total;
84 		if (!value)
88 		value = i915->params.enable_hangcheck &&
90 		if (value && intel_has_reset_engine(to_gt(i915)))
91 			value = 2;
94 		value = 0;
97 		value = HAS_POOLED_EU(i915);
100 		value = sseu->min_eu_in_pool;
105 			value = intel_huc_check_status(&i915->media_gt->uc.huc);
107 			value = intel_huc_check_status(&to_gt(i915)->uc.huc);
108 		if (value < 0)
109 			return value;
112 		value = intel_pxp_get_readiness_status(i915->pxp, 0);
113 		if (value < 0)
114 			return value;
118 		 * earlier versions as 0, in effect their value is undefined as
121 		value = i915_gem_mmap_gtt_version();
124 		value = i915->caps.scheduler;
153 		 * features this value needs to be provided from
156 		value = 1;
159 		value = intel_engines_has_context_isolation(i915);
166 		value = sseu->slice_mask;
167 		if (!value)
176 		value = intel_sseu_get_hsw_subslices(sseu, 0);
177 		if (!value)
181 		value = to_gt(i915)->clock_frequency;
184 		value = INTEL_INFO(i915)->has_coherent_ggtt;
187 		value = i915_perf_ioctl_version(i915);
190 		value = i915_perf_oa_timestamp_frequency(i915);
197 	if (put_user(value, param->value))