gt/uc/intel_guc_ads.c

64 	struct guc_mmio_reg regset[];
103 	return offsetof(struct __guc_ads_blob, regset);
255 __mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
257 	u32 pos = regset->storage_used;
260 	if (pos >= regset->storage_max) {
262 		struct guc_mmio_reg *r = krealloc(regset->storage,
265 			WARN_ONCE(1, "Incomplete regset list: can't add register (%d)\n",
270 		regset->registers = r + (regset->registers - regset->storage);
271 		regset->storage = r;
272 		regset->storage_max = size / sizeof(*slot);
275 	slot = &regset->storage[pos];
276 	regset->storage_used++;
283 					  struct temp_regset *regset,
286 	u32 count = regset->storage_used - (regset->registers - regset->storage);
299 	if (bsearch(&entry, regset->registers, count,
303 	slot = __mmio_reg_add(regset, &entry);
307 	while (slot-- > regset->registers) {
318 #define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \
320 			 regset, \
331 					 struct temp_regset *regset,
347 	return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);
350 #define GUC_MCR_REG_ADD(gt, regset, reg, masked) \
352 			 regset, \
356 static int guc_mmio_regset_init(struct temp_regset *regset,
370 	regset->registers = regset->storage + regset->storage_used;
372 	ret |= GUC_MMIO_REG_ADD(gt, regset, RING_MODE_GEN7(base), true);
373 	ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false);
374 	ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false);
378 		ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true);
386 		ret |= GUC_MCR_REG_ADD(gt, regset, wa->mcr_reg, wa->masked_reg);
390 		ret |= GUC_MMIO_REG_ADD(gt, regset,
397 			ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
399 			ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
402 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL0)), false);
403 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL1)), false);
404 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL2)), false);
405 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL3)), false);
406 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL4)), false);
407 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL5)), false);
408 		ret |= GUC_MCR_REG_ADD(gt, regset, MCR_REG(i915_mmio_reg_offset(EU_PERF_CNTL6)), false);
436 	guc_dbg(guc, "Used %zu KB for temporary ADS regset\n",