Lines Matching defs:cs
34 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value)
36 *cs++ = MI_SEMAPHORE_WAIT |
40 *cs++ = value;
41 *cs++ = offset;
42 *cs++ = 0;
44 return cs;
47 static u32 *emit_store(u32 *cs, u32 offset, u32 value)
49 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
50 *cs++ = offset;
51 *cs++ = 0;
52 *cs++ = value;
54 return cs;
57 static u32 *emit_srm(u32 *cs, i915_reg_t reg, u32 offset)
59 *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
60 *cs++ = i915_mmio_reg_offset(reg);
61 *cs++ = offset;
62 *cs++ = 0;
64 return cs;
80 u32 *cs;
86 cs = intel_ring_begin(rq, 28);
87 if (IS_ERR(cs)) {
89 return PTR_ERR(cs);
93 cs = emit_store(cs, offset + 4008, 1);
94 cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);
96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000);
97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004);
100 cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);
102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016);
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012);
105 intel_ring_advance(rq, cs);