Lines Matching defs:uncore
48 return rps_to_gt(rps)->uncore;
70 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
72 intel_uncore_write_fw(uncore, reg, val);
207 intel_uncore_write(gt->uncore,
240 intel_uncore_write(gt->uncore,
278 struct intel_uncore *uncore = rps_to_uncore(rps);
298 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
316 struct intel_uncore *uncore =
335 total = intel_uncore_read(uncore, DMIEC);
336 total += intel_uncore_read(uncore, DDREC);
337 total += intel_uncore_read(uncore, CSIEC);
351 static unsigned long ips_mch_val(struct intel_uncore *uncore)
356 tsfs = intel_uncore_read(uncore, TSFS);
357 x = intel_uncore_read8(uncore, TR1);
388 struct intel_uncore *uncore =
403 count = intel_uncore_read(uncore, GFXEC);
432 struct intel_uncore *uncore = rps_to_uncore(rps);
437 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
451 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
452 intel_uncore_posting_read16(uncore, MEMSWCTL);
455 intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);
483 static unsigned int init_emon(struct intel_uncore *uncore)
489 intel_uncore_write(uncore, ECR, 0);
490 intel_uncore_posting_read(uncore, ECR);
493 intel_uncore_write(uncore, SDEW, 0x15040d00);
494 intel_uncore_write(uncore, CSIEW0, 0x007f0000);
495 intel_uncore_write(uncore, CSIEW1, 0x1e220004);
496 intel_uncore_write(uncore, CSIEW2, 0x04000004);
499 intel_uncore_write(uncore, PEW(i), 0);
501 intel_uncore_write(uncore, DEW(i), 0);
505 u32 pxvidfreq = intel_uncore_read(uncore, PXVFREQ(i));
521 intel_uncore_write(uncore, PXW(i),
529 intel_uncore_write(uncore, OGW0, 0);
530 intel_uncore_write(uncore, OGW1, 0);
531 intel_uncore_write(uncore, EG0, 0x00007f00);
532 intel_uncore_write(uncore, EG1, 0x0000000e);
533 intel_uncore_write(uncore, EG2, 0x000e0000);
534 intel_uncore_write(uncore, EG3, 0x68000300);
535 intel_uncore_write(uncore, EG4, 0x42000000);
536 intel_uncore_write(uncore, EG5, 0x00140031);
537 intel_uncore_write(uncore, EG6, 0);
538 intel_uncore_write(uncore, EG7, 0);
541 intel_uncore_write(uncore, PXWL(i), 0);
544 intel_uncore_write(uncore, ECR, 0x80000019);
546 return intel_uncore_read(uncore, LCFUSE02) & LCFUSE_HIV_MASK;
552 struct intel_uncore *uncore = rps_to_uncore(rps);
558 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
561 intel_uncore_write16(uncore, PMMISC,
562 intel_uncore_read16(uncore, PMMISC) | MCPPCE_EN);
563 intel_uncore_write16(uncore, TSC1,
564 intel_uncore_read16(uncore, TSC1) | TSE);
567 intel_uncore_write(uncore, RCUPEI, 100000);
568 intel_uncore_write(uncore, RCDNEI, 100000);
571 intel_uncore_write(uncore, RCBMAXAVG, 90000);
572 intel_uncore_write(uncore, RCBMINAVG, 80000);
574 intel_uncore_write(uncore, MEMIHYST, 1);
580 vstart = (intel_uncore_read(uncore, PXVFREQ(fstart)) &
583 intel_uncore_write(uncore,
587 intel_uncore_write(uncore, VIDSTART, vstart);
588 intel_uncore_posting_read(uncore, VIDSTART);
591 intel_uncore_write(uncore, MEMMODECTL, rgvmodectl);
593 if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) &
595 drm_err(&uncore->i915->drm,
601 rps->ips.last_count1 = intel_uncore_read(uncore, DMIEC);
602 rps->ips.last_count1 += intel_uncore_read(uncore, DDREC);
603 rps->ips.last_count1 += intel_uncore_read(uncore, CSIEC);
606 rps->ips.last_count2 = intel_uncore_read(uncore, GFXEC);
615 rps->ips.corr = init_emon(uncore);
623 struct intel_uncore *uncore = rps_to_uncore(rps);
632 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
635 intel_uncore_rmw(uncore, MEMINTREN, MEMINT_EVAL_CHG_EN, 0);
636 intel_uncore_write(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
642 intel_uncore_write(uncore, MEMSWCTL, rgvswctl);
676 struct intel_uncore *uncore = gt->uncore;
714 set(uncore, GEN6_RP_UP_EI,
716 set(uncore, GEN6_RP_UP_THRESHOLD,
720 set(uncore, GEN6_RP_DOWN_EI,
722 set(uncore, GEN6_RP_DOWN_THRESHOLD,
727 set(uncore, GEN6_RP_CONTROL,
797 struct intel_uncore *uncore = rps_to_uncore(rps);
811 set(uncore, GEN6_RPNSWREQ, swreq);
1075 struct intel_uncore *uncore = rps_to_uncore(rps);
1077 set(uncore,
1080 set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val));
1091 struct intel_uncore *uncore = rps_to_uncore(rps);
1094 return intel_uncore_read(uncore, BXT_RP_STATE_CAP);
1096 return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
1102 struct intel_uncore *uncore = rps_to_uncore(rps);
1104 intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP) :
1105 intel_uncore_read(uncore, MTL_RP_STATE_CAP);
1107 intel_uncore_read(uncore, MTL_MPE_FREQUENCY) :
1108 intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY);
1133 intel_uncore_read(to_gt(i915)->uncore,
1191 if (snb_pcode_read(rps_to_gt(rps)->uncore,
1223 struct intel_uncore *uncore = gt->uncore;
1227 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
1230 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 0xa);
1239 struct intel_uncore *uncore = rps_to_uncore(rps);
1241 intel_uncore_write_fw(uncore, GEN6_RC_VIDEO_FREQ,
1244 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1253 struct intel_uncore *uncore = rps_to_uncore(rps);
1256 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 50000);
1257 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1328 struct intel_uncore *uncore = rps_to_uncore(rps);
1333 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000);
1334 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400);
1335 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000);
1336 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000);
1337 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000);
1339 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1342 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL,
1432 struct intel_uncore *uncore = rps_to_uncore(rps);
1436 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_TIMEOUT, 1000000);
1437 intel_uncore_write_fw(uncore, GEN6_RP_UP_THRESHOLD, 59400);
1438 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_THRESHOLD, 245000);
1439 intel_uncore_write_fw(uncore, GEN6_RP_UP_EI, 66000);
1440 intel_uncore_write_fw(uncore, GEN6_RP_DOWN_EI, 350000);
1442 intel_uncore_write_fw(uncore, GEN6_RP_IDLE_HYSTERSIS, 10);
1444 intel_uncore_write_fw(uncore, GEN6_RP_CONTROL,
1479 struct intel_uncore *uncore = rps_to_uncore(rps);
1486 pxvid = intel_uncore_read(uncore, PXVFREQ(rps->cur_freq));
1495 t = ips_mch_val(uncore);
1530 struct intel_uncore *uncore = rps_to_uncore(rps);
1541 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
1558 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1756 static void vlv_c0_read(struct intel_uncore *uncore, struct intel_rps_ei *ei)
1759 ei->render_c0 = intel_uncore_read(uncore, VLV_RENDER_C0_COUNT);
1760 ei->media_c0 = intel_uncore_read(uncore, VLV_MEDIA_C0_COUNT);
1765 struct intel_uncore *uncore = rps_to_uncore(rps);
1773 vlv_c0_read(uncore, &now);
1942 struct intel_uncore *uncore = rps_to_uncore(rps);
1948 intel_uncore_write16(uncore,
1950 intel_uncore_read(uncore, MEMINTRSTS));
1952 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
1953 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);
1954 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);
1955 max_avg = intel_uncore_read(uncore, RCBMAXAVG);
1956 min_avg = intel_uncore_read(uncore, RCBMINAVG);
2011 snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, ¶ms, NULL);
2069 return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
2098 struct intel_uncore *uncore = rps_to_uncore(rps);
2121 freq = take_fw ? intel_uncore_read(uncore, r) : intel_uncore_read_fw(uncore, r);
2150 struct intel_uncore *uncore = rps_to_uncore(rps);
2156 freq = intel_uncore_read(uncore, GEN6_RPNSWREQ);
2252 struct intel_uncore *uncore = gt->uncore;
2263 rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
2266 gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
2268 gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
2271 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2273 reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
2285 rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
2286 rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
2287 rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
2290 rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
2291 rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
2292 rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
2293 rpcurdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
2294 rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
2295 rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
2297 rpupei = intel_uncore_read(uncore, GEN6_RP_UP_EI);
2298 rpupt = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
2300 rpdownei = intel_uncore_read(uncore, GEN6_RP_DOWN_EI);
2301 rpdownt = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
2305 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2308 pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
2309 pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
2317 pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
2318 pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
2319 pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
2320 pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
2322 pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
2323 pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
2324 pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
2325 pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
2327 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
2414 struct intel_uncore *uncore = gt->uncore;
2419 pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
2635 struct intel_uncore *uncore = rps_to_uncore(rps);
2639 intel_uncore_write(uncore, GEN6_RP_CONTROL, state);
2644 struct intel_uncore *uncore = rps_to_uncore(rps);
2655 intel_uncore_write(uncore, GEN6_RPNSWREQ,
2669 struct intel_uncore *uncore = rps_to_uncore(rps);
2680 intel_uncore_write(uncore, GEN6_RPNSWREQ,
2698 with_intel_runtime_pm(gt->uncore->rpm, wakeref)
2699 val = intel_uncore_read(gt->uncore, reg32);