Lines Matching defs:set
70 static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
112 * dependent operations across a set of engines, such that
653 * Only set the down limit when we've reached the lowest level to avoid
714 set(uncore, GEN6_RP_UP_EI,
716 set(uncore, GEN6_RP_UP_THRESHOLD,
720 set(uncore, GEN6_RP_DOWN_EI,
722 set(uncore, GEN6_RP_DOWN_THRESHOLD,
727 set(uncore, GEN6_RP_CONTROL,
811 set(uncore, GEN6_RPNSWREQ, swreq);
813 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d, swreq:%x\n",
828 GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n",
1077 set(uncore,
1080 set(uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, val));
1588 set(rps_to_uncore(rps), GEN6_RP_CONTROL, 0);
1880 drm_dbg(&i915->drm, "Failed to set new GPU frequency\n");
2740 * set up, to avoid intel-ips sneaking in and reading bogus values.