i915/gt/intel_rps.c

53 	struct intel_gt *gt = rps_to_gt(rps);
55 	return &gt->uc.guc.slpc;
60 	struct intel_gt *gt = rps_to_gt(rps);
62 	return intel_uc_uses_guc_slpc(&gt->uc);
78 	struct intel_gt *gt = rps_to_gt(rps);
85 	for_each_engine(engine, gt, id) {
129 		GT_TRACE(gt,
139 			queue_work(gt->i915->unordered_wq, &rps->work);
144 			queue_work(gt->i915->unordered_wq, &rps->work);
194 	struct intel_gt *gt = rps_to_gt(rps);
198 	GT_TRACE(gt, "interrupts:on rps->pm_events: %x, rps_pm_mask:%x\n",
203 	spin_lock_irq(gt->irq_lock);
204 	gen6_gt_pm_enable_irq(gt, rps->pm_events);
205 	spin_unlock_irq(gt->irq_lock);
207 	intel_uncore_write(gt->uncore,
224 	struct intel_gt *gt = rps_to_gt(rps);
226 	spin_lock_irq(gt->irq_lock);
227 	if (GRAPHICS_VER(gt->i915) >= 11)
233 	spin_unlock_irq(gt->irq_lock);
238 	struct intel_gt *gt = rps_to_gt(rps);
240 	intel_uncore_write(gt->uncore,
243 	spin_lock_irq(gt->irq_lock);
244 	gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
245 	spin_unlock_irq(gt->irq_lock);
247 	intel_synchronize_irq(gt->i915);
258 	GT_TRACE(gt, "interrupts:off\n");
675 	struct intel_gt *gt = rps_to_gt(rps);
676 	struct intel_uncore *uncore = gt->uncore;
705 	if (IS_VALLEYVIEW(gt->i915))
708 	GT_TRACE(gt,
715 	    intel_gt_ns_to_pm_interval(gt, ei_up * 1000));
717 	    intel_gt_ns_to_pm_interval(gt,
721 	    intel_gt_ns_to_pm_interval(gt, ei_down * 1000));
723 	    intel_gt_ns_to_pm_interval(gt,
728 	    (GRAPHICS_VER(gt->i915) > 9 ? 0 : GEN6_RP_MEDIA_TURBO) |
1018 		struct intel_rps *rps = &READ_ONCE(rq->engine)->gt->rps;
1222 	struct intel_gt *gt = rps_to_gt(rps);
1223 	struct intel_uncore *uncore = gt->uncore;
1226 	if (GRAPHICS_VER(gt->i915) == 9)
1269 	struct intel_gt *gt = rps_to_gt(rps);
1274 	switch (gt->info.sseu.eu_total) {
1806 	struct intel_gt *gt = rps_to_gt(rps);
1812 	spin_lock_irq(gt->irq_lock);
1815 	spin_unlock_irq(gt->irq_lock);
1836 	GT_TRACE(gt,
1848 			adj = IS_CHERRYVIEW(gt->i915) ? 2 : 1;
1864 			adj = IS_CHERRYVIEW(gt->i915) ? -2 : -1;
1888 	spin_lock_irq(gt->irq_lock);
1889 	gen6_gt_pm_unmask_irq(gt, rps->pm_events);
1890 	spin_unlock_irq(gt->irq_lock);
1895 	struct intel_gt *gt = rps_to_gt(rps);
1898 	lockdep_assert_held(gt->irq_lock);
1903 	GT_TRACE(gt, "irq events:%x\n", events);
1905 	gen6_gt_pm_mask_irq(gt, events);
1908 	queue_work(gt->i915->unordered_wq, &rps->work);
1913 	struct intel_gt *gt = rps_to_gt(rps);
1918 		spin_lock(gt->irq_lock);
1920 		GT_TRACE(gt, "irq events:%x\n", events);
1922 		gen6_gt_pm_mask_irq(gt, events);
1925 		queue_work(gt->i915->unordered_wq, &rps->work);
1926 		spin_unlock(gt->irq_lock);
1929 	if (GRAPHICS_VER(gt->i915) >= 8)
1933 		intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10);
2250 	struct intel_gt *gt = rps_to_gt(rps);
2251 	struct drm_i915_private *i915 = gt->i915;
2252 	struct intel_uncore *uncore = gt->uncore;
2358 		   intel_gt_pm_interval_to_ns(gt, rpcurupei));
2360 		   rpcurup, intel_gt_pm_interval_to_ns(gt, rpcurup));
2362 		   rpprevup, intel_gt_pm_interval_to_ns(gt, rpprevup));
2366 		   rpupei, intel_gt_pm_interval_to_ns(gt, rpupei));
2368 		   rpupt, intel_gt_pm_interval_to_ns(gt, rpupt));
2372 		   intel_gt_pm_interval_to_ns(gt, rpcurdownei));
2375 		   intel_gt_pm_interval_to_ns(gt, rpcurdown));
2378 		   intel_gt_pm_interval_to_ns(gt, rpprevdown));
2382 		   rpdownei, intel_gt_pm_interval_to_ns(gt, rpdownei));
2384 		   rpdownt, intel_gt_pm_interval_to_ns(gt, rpdownt));
2413 	struct intel_gt *gt = rps_to_gt(rps);
2414 	struct intel_uncore *uncore = gt->uncore;
2694 	struct intel_gt *gt = rps_to_gt(rps);
2698 	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
2699 		val = intel_uncore_read(gt->uncore, reg32);
2736 	struct intel_gt *gt = rps_to_gt(rps);
2742 	if (GRAPHICS_VER(gt->i915) == 5) {
2744 		rcu_assign_pointer(ips_mchdev, gt->i915);