Lines Matching defs:cs

659 	u32 *cs;
661 cs = intel_ring_begin(rq, 12);
662 if (IS_ERR(cs))
663 return PTR_ERR(cs);
665 *cs++ = MI_LOAD_REGISTER_IMM(1);
666 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
667 *cs++ = valid;
669 *cs++ = MI_LOAD_REGISTER_IMM(1);
670 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
671 *cs++ = pp_dir(vm);
674 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
675 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
676 *cs++ = intel_gt_scratch_offset(engine->gt,
679 *cs++ = MI_LOAD_REGISTER_IMM(1);
680 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
681 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
683 intel_ring_advance(rq, cs);
699 u32 *cs;
713 cs = intel_ring_begin(rq, len);
714 if (IS_ERR(cs))
715 return PTR_ERR(cs);
719 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
723 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
728 *cs++ = i915_mmio_reg_offset(
730 *cs++ = _MASKED_BIT_ENABLE(
741 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
757 *cs++ = MI_SET_CONTEXT;
758 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |
763 *cs++ = MI_NOOP;
764 *cs++ = MI_SET_CONTEXT;
765 *cs++ = i915_ggtt_offset(ce->state) | flags;
770 *cs++ = MI_NOOP;
777 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
783 *cs++ = i915_mmio_reg_offset(last_reg);
784 *cs++ = _MASKED_BIT_DISABLE(
789 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
790 *cs++ = i915_mmio_reg_offset(last_reg);
791 *cs++ = intel_gt_scratch_offset(engine->gt,
793 *cs++ = MI_NOOP;
795 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
797 *cs++ = MI_SUSPEND_FLUSH;
800 intel_ring_advance(rq, cs);
808 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
814 cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2);
815 if (IS_ERR(cs))
816 return PTR_ERR(cs);
823 *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW);
825 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
826 *cs++ = remap_info[i];
828 *cs++ = MI_NOOP;
829 intel_ring_advance(rq, cs);