i915/gt/intel_reset.c

59 		drm_dbg(&ctx->i915->drm,
92 	drm_notice(&ctx->i915->drm,
107 		drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
162 	struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
191 	struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
201 	struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
291 	loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1;
439 		    GRAPHICS_VER(engine->i915) != 12)
649 	if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES)
652 	if (GRAPHICS_VER(gt->i915) >= 11)
679 	struct drm_i915_private *i915 = gt->i915;
683 	else if (GRAPHICS_VER(i915) >= 8)
685 	else if (GRAPHICS_VER(i915) >= 6)
687 	else if (GRAPHICS_VER(i915) >= 5)
689 	else if (IS_G4X(i915))
691 	else if (IS_G33(i915) || IS_PINEVIEW(i915))
693 	else if (GRAPHICS_VER(i915) >= 3)
702 		GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
709 	if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
800 	if (!gt->i915->params.reset)
808 	if (gt->i915->params.reset < 2)
811 	return INTEL_INFO(gt->i915)->has_reset_engine;
818 	GEM_BUG_ON(!HAS_GT_UC(gt->i915));
869 		unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
918 	err = i915_ggtt_enable_hw(gt->i915);
989 	if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1027 		struct drm_printer p = drm_dbg_printer(&gt->i915->drm,
1099 	ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
1100 	if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1107 		add_taint_for_CI(gt->i915, TAINT_WARN);
1112 	 * Undo nop_submit_request. We prevent all new i915 requests from
1214 	atomic_inc(&gt->i915->gpu_error.reset_count);
1219 		if (gt->i915->params.reset)
1226 	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1227 		intel_runtime_pm_disable_interrupts(gt->i915);
1234 	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1235 		intel_runtime_pm_enable_interrupts(gt->i915);
1237 	intel_overlay_reset(gt->i915);
1279 	add_taint_for_CI(gt->i915, TAINT_WARN);
1330 		drm_notice(&engine->i915->drm,
1332 	i915_increase_reset_engine_count(&engine->i915->gpu_error, engine);
1390 	struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1403 		intel_display_reset_prepare(gt->i915);
1407 		intel_display_reset_finish(gt->i915);
1501 	 * submission the GuC owns the per-engine reset, not the i915.
1597 	i915_disable_error_state(gt->i915, -ENODEV);
1601 	add_taint_for_CI(gt->i915, TAINT_WARN);
1607 	i915_disable_error_state(gt->i915, -ENODEV);
1627 	i915_gem_shrinker_taints_mutex(gt->i915, &gt->reset.mutex);
1655 	queue_delayed_work(gt->i915->unordered_wq, &w->work, timeout);
1671 	if (GRAPHICS_VER(gt->i915) < 11)
1677 	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))