i915/gt/intel_reset.c

276 	 * On some platforms, e.g. Jasperlake, we see that the engine register
283 	 * engine state is still in flux and not ready for resuming.
313 	 * As we have observed that the engine state is still volatile
325 	struct intel_engine_cs *engine;
334 		for_each_engine_masked(engine, gt, engine_mask, tmp) {
335 			hw_mask |= engine->reset_domain;
356 static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
360 	GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
362 	vecs_id = _VECS((engine->instance) / 2);
364 	return engine->gt->engine[vecs_id];
377 static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
380 	switch (engine->class) {
382 		MISSING_CASE(engine->class);
385 		sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base);
388 		sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);
391 		sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);
393 		sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
397 		sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base);
400 		sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base);
403 		sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base);
405 		sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
411 static int gen11_lock_sfc(struct intel_engine_cs *engine,
415 	struct intel_uncore *uncore = engine->uncore;
416 	u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
421 	switch (engine->class) {
423 		if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
428 		get_sfc_forced_lock_data(engine, &sfc_lock);
438 		if (engine->class != VIDEO_DECODE_CLASS ||
439 		    GRAPHICS_VER(engine->i915) != 12)
447 		 * forced lock on the VE engine that shares the same SFC.
450 					   GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) &
454 		paired_vecs = find_sfc_paired_vecs_engine(engine);
459 		*unlock_mask |= engine->mask;
463 	 * If the engine is using an SFC, tell the engine that a software reset
464 	 * is going to happen. The engine will then try to force lock the SFC.
465 	 * If SFC ends up being locked to the engine we want to reset, we have
480 	 * We should reset both the engine and the SFC if:
481 	 *  - We were locking the SFC to this engine and the lock succeeded
483 	 *  - We were locking the SFC to a different engine (Wa_14010733141)
486 	 * Otherwise we need only reset the engine by itself and we can
495 		ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
503 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
505 	struct intel_uncore *uncore = engine->uncore;
506 	u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
509 	if (engine->class != VIDEO_DECODE_CLASS &&
510 	    engine->class != VIDEO_ENHANCEMENT_CLASS)
513 	if (engine->class == VIDEO_DECODE_CLASS &&
514 	    (BIT(engine->instance) & vdbox_sfc_access) == 0)
517 	get_sfc_forced_lock_data(engine, &sfc_lock);
526 	struct intel_engine_cs *engine;
535 		for_each_engine_masked(engine, gt, engine_mask, tmp) {
536 			reset_mask |= engine->reset_domain;
537 			ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
552 	 * Due to Wa_14010733141, we may have locked an SFC to an engine that
557 	for_each_engine_masked(engine, gt, unlock_mask, tmp)
558 		gen11_unlock_sfc(engine);
563 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
565 	struct intel_uncore *uncore = engine->uncore;
566 	const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
570 	if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
596 		gt_err(engine->gt,
598 		       engine->name, request,
604 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
606 	intel_uncore_write_fw(engine->uncore,
607 			      RING_RESET_CTL(engine->mmio_base),
615 	struct intel_engine_cs *engine;
623 	for_each_engine_masked(engine, gt, engine_mask, tmp) {
624 		ret = gen8_engine_reset_prepare(engine);
658 	for_each_engine_masked(engine, gt, engine_mask, tmp)
659 		gen8_engine_reset_cancel(engine);
726 	 * we're going to do a GSC engine reset and then wait for 200ms for the
731 	 * Skipping the GSC engine is safe because, differently from other
738 	if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) {
831 static void reset_prepare_engine(struct intel_engine_cs *engine)
834 	 * During the reset sequence, we must prevent the engine from
836 	 * the engine, if it does enter RC6 during the reset, the state
840 	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
841 	if (engine->reset.prepare)
842 		engine->reset.prepare(engine);
878 	struct intel_engine_cs *engine;
887 	 * sanitized, do that after engine reset. reset_prepare()
888 	 * is followed by engine reset which in this mode requires GuC to
894 	for_each_engine(engine, gt, id) {
895 		if (intel_engine_pm_get_if_awake(engine))
896 			awake |= engine->mask;
897 		reset_prepare_engine(engine);
910 	struct intel_engine_cs *engine;
923 	for_each_engine(engine, gt, id)
924 		__intel_engine_reset(engine, stalled_mask & engine->mask);
934 static void reset_finish_engine(struct intel_engine_cs *engine)
936 	if (engine->reset.finish)
937 		engine->reset.finish(engine);
938 	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
940 	intel_engine_signal_breadcrumbs(engine);
945 	struct intel_engine_cs *engine;
948 	for_each_engine(engine, gt, id) {
949 		reset_finish_engine(engine);
950 		if (awake & engine->mask)
951 			intel_engine_pm_put(engine);
964 		intel_engine_signal_breadcrumbs(request->engine);
972 	struct intel_engine_cs *engine;
992 	for_each_engine(engine, gt, id)
993 		engine->submit_request = nop_submit_request;
1005 	for_each_engine(engine, gt, id)
1006 		if (engine->reset.cancel)
1007 			engine->reset.cancel(engine);
1029 		struct intel_engine_cs *engine;
1033 		for_each_engine(engine, gt, id) {
1034 			if (intel_engine_is_idle(engine))
1037 			intel_engine_dump(engine, &p, "%s\n", engine->name);
1116 	 * engine->submit_request() as we swap over. So unlike installing
1158 	struct intel_engine_cs *engine;
1162 	for_each_engine(engine, gt, id) {
1163 		ret = intel_engine_resume(engine);
1239 	/* sanitize uC after engine reset */
1300  * intel_gt_reset_engine() - Reset a specific engine within a gt.
1301  * @engine: engine to be reset.
1303  * This function resets the specified engine within a gt.
1308 int intel_gt_reset_engine(struct intel_engine_cs *engine)
1310 	return __intel_gt_reset(engine->gt, engine->mask);
1313 int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1315 	struct intel_gt *gt = engine->gt;
1318 	ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1319 	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1321 	if (intel_engine_uses_guc(engine))
1324 	if (!intel_engine_pm_get_if_awake(engine))
1327 	reset_prepare_engine(engine);
1330 		drm_notice(&engine->i915->drm,
1331 			   "Resetting %s for %s\n", engine->name, msg);
1332 	i915_increase_reset_engine_count(&engine->i915->gpu_error, engine);
1334 	ret = intel_gt_reset_engine(engine);
1337 		ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);
1346 	__intel_engine_reset(engine, true);
1349 	 * The engine and its registers (and workarounds in case of render)
1353 	ret = intel_engine_resume(engine);
1356 	intel_engine_cancel_stop_cs(engine);
1357 	reset_finish_engine(engine);
1358 	intel_engine_pm_put_async(engine);
1363  * intel_engine_reset - reset GPU engine to recover from a hang
1364  * @engine: engine to reset
1367  * Reset a specific GPU engine. Useful if a hang is detected.
1372  *  - reset engine (which will force the engine to idle)
1373  *  - re-init/configure engine
1375 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1380 	err = __intel_engine_reset_bh(engine, msg);
1432 	struct intel_engine_cs *engine;
1465 	 * Try engine reset when available. We fall back to full reset if
1471 		for_each_engine_masked(engine, gt, engine_mask, tmp) {
1473 			if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1477 			if (__intel_engine_reset_bh(engine, msg) == 0)
1478 				engine_mask &= ~engine->mask;
1480 			clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1500 	 * Prevent any other reset-engine attempt. We don't do this for GuC
1501 	 * submission the GuC owns the per-engine reset, not the i915.
1504 		for_each_engine(engine, gt, tmp) {
1505 			while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1508 					    I915_RESET_ENGINE + engine->id,
1519 		for_each_engine(engine, gt, tmp)
1520 			clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1667  * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.