i915/gt/intel_rc6.c

48 	return rc6_to_gt(rc)->uncore;
59 	struct intel_uncore *uncore = gt->uncore;
70 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
71 		intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
73 		intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
74 		intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
76 			intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
78 		intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
80 		intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
82 		intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
103 	intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
104 	intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
143 	intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
148 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
154 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
155 		intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
161 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
163 		intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
166 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
167 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
169 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
171 	intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
173 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
196 	intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
197 	intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
200 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
212 		intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
218 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
223 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
224 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
225 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
227 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
228 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
229 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
240 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
247 	intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
248 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
249 	intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
250 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
251 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
254 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
256 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
257 	intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
258 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
259 	intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
260 	intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
274 	ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
284 		ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
294 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
300 	pcbr = intel_uncore_read(uncore, VLV_PCBR);
307 		intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
316 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
322 	pcbr = intel_uncore_read(uncore, VLV_PCBR);
360 	intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
369 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
374 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
375 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
376 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
379 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
380 	intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
383 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
386 	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
397 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
401 	intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
402 	intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
403 	intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
406 		intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
408 	intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
411 	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
425 		struct intel_uncore *uncore = rc6_to_uncore(rc6);
428 		with_intel_runtime_pm(uncore->rpm, wakeref)
429 			rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
439 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
444 	rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL);
445 	rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE);
454 	if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
464 		intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
471 	if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
472 	      (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
473 	      (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
474 	      (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
480 	if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) ||
481 	    !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) ||
482 	    !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) {
487 	if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) {
492 	if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) {
568 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
574 	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
576 		intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
577 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
578 	intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
579 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
645 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
652 	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
671 	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
683 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
689 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
694 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
709 	intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
717 	intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
734 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
740 		intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
750 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
757 	 * uncore lock to prevent concurrent access to range reg.
759 	lockdep_assert_held(&uncore->lock);
771 	intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
773 	upper = intel_uncore_read_fw(uncore, reg);
777 		intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
779 		lower = intel_uncore_read_fw(uncore, reg);
781 		intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
783 		upper = intel_uncore_read_fw(uncore, reg);
798 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
808 	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
810 	spin_lock_irqsave(&uncore->lock, flags);
811 	intel_uncore_forcewake_get__locked(uncore, fw_domains);
818 		time_hw = vlv_residency_raw(uncore, reg);
830 		time_hw = intel_uncore_read_fw(uncore, reg);
852 	intel_uncore_forcewake_put__locked(uncore, fw_domains);
853 	spin_unlock_irqrestore(&uncore->lock, flags);
870 	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
872 			   intel_uncore_read(gt->uncore, reg),