i915/gt/intel_gtt.c

104 	type = intel_gt_coherent_map_type(vm->gt, obj, true);
128 	type = intel_gt_coherent_map_type(vm->gt, obj, true);
435 void gtt_write_workarounds(struct intel_gt *gt)
437 	struct drm_i915_private *i915 = gt->i915;
438 	struct intel_uncore *uncore = gt->uncore;
497 		gt_WARN_ON_ONCE(gt, can_use_gtt_cache &&
522 static void xelpg_setup_private_ppat(struct intel_gt *gt)
524 	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0),
526 	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1),
528 	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2),
530 	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3),
532 	intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4),
554 static void xehp_setup_private_ppat(struct intel_gt *gt)
559 	fw = intel_uncore_forcewake_for_reg(gt->uncore, _MMIO(XEHP_PAT_INDEX(0).reg),
561 	intel_uncore_forcewake_get(gt->uncore, fw);
563 	intel_gt_mcr_lock(gt, &flags);
564 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
565 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
566 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
567 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
568 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
569 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
570 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
571 	intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
572 	intel_gt_mcr_unlock(gt, flags);
574 	intel_uncore_forcewake_put(gt->uncore, fw);
669 void setup_private_pat(struct intel_gt *gt)
671 	struct intel_uncore *uncore = gt->uncore;
672 	struct drm_i915_private *i915 = gt->i915;
676 	if (gt->type == GT_MEDIA) {
677 		xelpmp_setup_private_ppat(gt->uncore);
682 		xelpg_setup_private_ppat(gt);
684 		xehp_setup_private_ppat(gt);