i915/gt/intel_ggtt_fencing.c

20  * Important to avoid confusions: "fences" in the i915 driver are not execution
51 	return fence->ggtt->vm.i915;
174 	struct drm_i915_private *i915 = fence_to_i915(fence);
182 	if (GRAPHICS_VER(i915) == 2)
184 	else if (GRAPHICS_VER(i915) == 3)
355 	if (intel_has_pending_fb_unpin(ggtt->vm.i915))
574 	struct drm_i915_private *i915 = ggtt->vm.i915;
578 	if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
588 	} else if (GRAPHICS_VER(i915) >= 6) {
589 		if (i915->preserve_bios_swizzle) {
620 	} else if (GRAPHICS_VER(i915) == 5) {
627 	} else if (GRAPHICS_VER(i915) == 2) {
634 	} else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) {
706 		if (GRAPHICS_VER(i915) == 4 &&
713 			drm_err(&i915->drm, "Couldn't read from MCHBAR.  "
732 		i915->gem_quirks |= GEM_QUIRK_PIN_SWIZZLED_PAGES;
737 	to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
738 	to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
765  * @obj: i915 GEM buffer object
802  * @obj: i915 GEM buffer object
840 	struct drm_i915_private *i915 = ggtt->vm.i915;
852 	else if (GRAPHICS_VER(i915) >= 7 &&
853 		 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
855 	else if (GRAPHICS_VER(i915) >= 4 ||
856 		 IS_I945G(i915) || IS_I945GM(i915) ||
857 		 IS_G33(i915) || IS_PINEVIEW(i915))
862 	if (intel_vgpu_active(i915))
900 	struct drm_i915_private *i915 = gt->i915;
903 	if (GRAPHICS_VER(i915) < 5 ||
904 	    to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
909 	if (GRAPHICS_VER(i915) == 5)
914 	if (GRAPHICS_VER(i915) == 6)
918 	else if (GRAPHICS_VER(i915) == 7)
922 	else if (GRAPHICS_VER(i915) == 8)
927 		MISSING_CASE(GRAPHICS_VER(i915));