i915/gt/intel_engine_cs.c

275 	struct intel_uncore *uncore = gt->uncore;
299 			cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
303 			cxt_size = intel_uncore_read(uncore, CXT_SIZE);
318 			cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
488 	engine->uncore = gt->uncore;
766 	media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
775 		fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
1001 	intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
1628 	struct intel_uncore *uncore = engine->uncore;
1632 	intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1639 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1642 	err = __intel_wait_for_register_fw(engine->uncore, mode,
1649 	intel_uncore_posting_read_fw(uncore, mode);
1726 	val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1740 	ret =  __intel_wait_for_register_fw(gt->uncore,
1773 	struct intel_uncore *uncore = engine->uncore;
1783 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1789 			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1792 				intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1794 				intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1817 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1823 			intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1825 			intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1827 			intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1830 			intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1834 				intel_uncore_read(uncore, GEN4_INSTDONE1);
1836 		instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
2418 	wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2421 		intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2554 	intel_uncore_write(engine->uncore, GEN12_RCU_MODE,