i915/gt/gen2_engine_cs.c

16 int gen2_emit_flush(struct i915_request *rq, u32 mode)
25 	cs = intel_ring_begin(rq, 2 + 4 * num_store_dw);
38 	intel_ring_advance(rq, cs);
43 int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
79 		if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
87 	cs = intel_ring_begin(rq, i);
105 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
115 		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
124 	intel_ring_advance(rq, cs);
129 int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode)
133 	cs = intel_ring_begin(rq, 2);
139 	intel_ring_advance(rq, cs);
144 static u32 *__gen2_emit_breadcrumb(struct i915_request *rq, u32 *cs,
147 	GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
148 	GEM_BUG_ON(offset_in_page(rq->hwsp_seqno) != I915_GEM_HWS_SEQNO_ADDR);
155 		*cs++ = rq->fence.seqno;
161 		*cs++ = rq->fence.seqno;
166 	rq->tail = intel_ring_offset(rq, cs);
167 	assert_ring_tail_valid(rq->ring, rq->tail);
172 u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs)
174 	return __gen2_emit_breadcrumb(rq, cs, 16, 8);
177 u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
179 	return __gen2_emit_breadcrumb(rq, cs, 8, 8);
186 int i830_emit_bb_start(struct i915_request *rq,
191 		intel_gt_scratch_offset(rq->engine->gt,
194 	GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
196 	cs = intel_ring_begin(rq, 6);
207 	intel_ring_advance(rq, cs);
213 		cs = intel_ring_begin(rq, 6 + 2);
231 		intel_ring_advance(rq, cs);
240 	cs = intel_ring_begin(rq, 2);
246 	intel_ring_advance(rq, cs);
251 int gen3_emit_bb_start(struct i915_request *rq,
260 	cs = intel_ring_begin(rq, 2);
266 	intel_ring_advance(rq, cs);
271 int gen4_emit_bb_start(struct i915_request *rq,
282 	cs = intel_ring_begin(rq, 2);
288 	intel_ring_advance(rq, cs);