Lines Matching defs:engine
105 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
115 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
147 GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt != rq->engine->status_page.vma);
191 intel_gt_scratch_offset(rq->engine->gt,
194 GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
293 void gen2_irq_enable(struct intel_engine_cs *engine)
295 struct drm_i915_private *i915 = engine->i915;
297 i915->irq_mask &= ~engine->irq_enable_mask;
299 ENGINE_POSTING_READ16(engine, RING_IMR);
302 void gen2_irq_disable(struct intel_engine_cs *engine)
304 struct drm_i915_private *i915 = engine->i915;
306 i915->irq_mask |= engine->irq_enable_mask;
310 void gen3_irq_enable(struct intel_engine_cs *engine)
312 engine->i915->irq_mask &= ~engine->irq_enable_mask;
313 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
314 intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
317 void gen3_irq_disable(struct intel_engine_cs *engine)
319 engine->i915->irq_mask |= engine->irq_enable_mask;
320 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
323 void gen5_irq_enable(struct intel_engine_cs *engine)
325 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
328 void gen5_irq_disable(struct intel_engine_cs *engine)
330 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);