i915/gem/i915_gem_stolen.c

208 	u32 reg_val = intel_uncore_read(uncore,
215 		IS_GM45(i915) ? "CTG" : "ELK", reg_val);
217 	if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0)
226 		 reg_val);
228 	if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK))
231 	*base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
233 		    (reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
243 	u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
245 	drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
247 	if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
250 	*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
252 	switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) {
267 		MISSING_CASE(reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK);
276 	u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
279 	drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
281 	if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
284 	switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
286 		MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);
305 	u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
307 	drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
309 	if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
312 	*base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;
314 	switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
323 		MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);
332 	u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
334 	drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
336 	if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
339 	*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
341 	switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
356 		MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
365 	u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED);
368 	drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val);
370 	if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE))
373 	if (!(reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK))
376 	*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
385 	u64 reg_val = intel_uncore_read64(uncore, GEN6_STOLEN_RESERVED);
387 	drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
410 	switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
425 		MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
432 		*base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;