Lines Matching refs:port
21 #define BXT_MIPI_DIV_SHIFT(port) \
22 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
28 #define BXT_MIPI_TX_ESCLK_SHIFT(port) \
29 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
33 #define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
34 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
36 #define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
37 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
41 #define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
42 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
46 #define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \
47 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \
49 #define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \
50 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port))
54 #define BXT_MIPI_8X_BY3_SHIFT(port) \
55 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \
59 #define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \
60 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \
62 #define BXT_MIPI_8X_BY3_DIVIDER(port, val) \
63 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port))
67 #define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \
68 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \
72 #define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \
73 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \
75 #define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \
76 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port))