i915/display/vlv_dsi_pll.c

60 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
71 		drm_err(&dev_priv->drm, "DSI CLK Out of Range\n");
75 	if (IS_CHERRYVIEW(dev_priv)) {
119 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
125 	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
150 		drm_err(&dev_priv->drm, "wrong P1 divisor\n");
160 		drm_err(&dev_priv->drm, "wrong m_seed programmed\n");
178 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
185 	ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
187 		drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n");
199 	drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n",
216 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
218 	drm_dbg_kms(&dev_priv->drm, "\n");
220 	vlv_cck_get(dev_priv);
222 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
223 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
224 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
232 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
234 	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
237 		vlv_cck_put(dev_priv);
238 		drm_err(&dev_priv->drm, "DSI PLL lock failed\n");
241 	vlv_cck_put(dev_priv);
243 	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");
248 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
251 	drm_dbg_kms(&dev_priv->drm, "\n");
253 	vlv_cck_get(dev_priv);
255 	tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
258 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
260 	vlv_cck_put(dev_priv);
263 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
270 	val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE);
284 	val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
285 	if (IS_GEMINILAKE(dev_priv)) {
287 			drm_dbg(&dev_priv->drm,
293 			drm_dbg(&dev_priv->drm,
304 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
306 	drm_dbg_kms(&dev_priv->drm, "\n");
308 	intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0);
314 	if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE,
316 		drm_err(&dev_priv->drm,
323 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
326 	drm_dbg_kms(&dev_priv->drm, "\n");
328 	vlv_cck_get(dev_priv);
329 	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
330 	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
331 	vlv_cck_put(dev_priv);
355 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
358 	config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL);
362 	drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk);
381 	struct drm_i915_private *dev_priv = to_i915(dev);
418 	intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1,
420 	intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2,
428 	struct drm_i915_private *dev_priv = to_i915(dev);
439 	tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL);
475 	intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp);
481 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
497 	if (IS_BROXTON(dev_priv)) {
506 		drm_err(&dev_priv->drm,
510 		drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n");
522 	if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
539 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
543 	drm_dbg_kms(&dev_priv->drm, "\n");
546 	intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
547 	intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL);
550 	if (IS_BROXTON(dev_priv)) {
558 	intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE);
561 	if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,
563 		drm_err(&dev_priv->drm,
568 	drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n");
574 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
578 	if (IS_BROXTON(dev_priv)) {