i915/display/vlv_dsi.c

253 static void band_gap_reset(struct drm_i915_private *dev_priv)
255 	vlv_flisdsi_get(dev_priv);
257 	vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
258 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
259 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
261 	vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
262 	vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
264 	vlv_flisdsi_put(dev_priv);
271 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
277 	drm_dbg_kms(&dev_priv->drm, "\n");
300 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
457 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
463 	vlv_flisdsi_get(dev_priv);
466 	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
467 	vlv_flisdsi_put(dev_priv);
470 	band_gap_reset(dev_priv);
497 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
499 	if (IS_GEMINILAKE(dev_priv))
501 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
570 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
577 		i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
596 		if ((IS_BROXTON(dev_priv) || port == PORT_A) &&
614 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
622 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
635 		i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
646 			if (IS_BROXTON(dev_priv))
666 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
671 		i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
732 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
741 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
747 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
755 	if (IS_BROXTON(dev_priv)) {
764 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
766 		intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),
770 	if (!IS_GEMINILAKE(dev_priv))
778 	if (IS_GEMINILAKE(dev_priv)) {
790 	if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
862 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
864 	if (IS_GEMINILAKE(dev_priv))
876 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
882 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
909 	if (IS_BROXTON(dev_priv)) {
919 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
924 		intel_de_rmw(display, DSPCLK_GATE_D(dev_priv),
941 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
949 	wakeref = intel_display_power_get_if_enabled(dev_priv,
959 	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
960 	    !bxt_dsi_pll_is_enabled(dev_priv))
965 		i915_reg_t port_ctrl = port_ctrl_reg(dev_priv, port);
973 		if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
990 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1008 	intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1178 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1182 	drm_dbg_kms(&dev_priv->drm, "\n");
1186 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1219 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1254 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1308 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1328 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1343 		} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1378 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
1425 		if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1462 		if (IS_GEMINILAKE(dev_priv)) {
1514 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1518 	if (IS_GEMINILAKE(dev_priv))
1525 		if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1597 	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
1646 	mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
1654 		drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
1675 		drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
1686 		drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
1696 		drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
1880 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1890 	drm_dbg_kms(&dev_priv->drm, "\n");
1893 	if (!intel_bios_is_dsi_present(dev_priv, &port))
1896 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1897 		dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
1899 		dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
1914 	drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_dsi_funcs,
1919 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1939 	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
1948 	intel_bios_init_panel_late(dev_priv, &connector->panel, NULL, NULL);
1955 	if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1958 	if (drm_WARN_ON(&dev_priv->drm, connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1974 		drm_dbg_kms(&dev_priv->drm, "no device found\n");
1981 		drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
1985 			drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
1997 	drm_connector_init(&dev_priv->drm, &connector->base, &intel_dsi_connector_funcs,
2006 	mutex_lock(&dev_priv->drm.mode_config.mutex);
2008 	mutex_unlock(&dev_priv->drm.mode_config.mutex);
2011 		drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");