i915/display/skl_scaler.c

111 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
133 	if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
135 		drm_dbg_kms(&dev_priv->drm,
155 			drm_dbg_kms(&dev_priv->drm,
167 		drm_dbg_kms(&dev_priv->drm,
177 	if (DISPLAY_VER(dev_priv) < 11) {
182 	} else if (DISPLAY_VER(dev_priv) < 12) {
187 	} else if (DISPLAY_VER(dev_priv) < 14) {
204 		drm_dbg_kms(&dev_priv->drm,
221 		drm_dbg_kms(&dev_priv->drm,
230 	drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
273 	struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
280 	if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
300 		drm_dbg_kms(&dev_priv->drm,
338 		if (DISPLAY_VER(dev_priv) >= 11)
342 		drm_dbg_kms(&dev_priv->drm,
358 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
374 	if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
384 		if (DISPLAY_VER(dev_priv) == 9) {
386 		} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
402 	} else if (DISPLAY_VER(dev_priv) >= 10) {
436 		if (DISPLAY_VER(dev_priv) >= 14) {
449 		} else if (DISPLAY_VER(dev_priv) >= 10 ||
468 			drm_dbg_kms(&dev_priv->drm,
478 	drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
487  * @dev_priv: i915 device
502 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
531 		drm_dbg_kms(&dev_priv->drm,
573 				if (DISPLAY_VER(dev_priv) >= 10)
576 				plane = drm_plane_from_index(&dev_priv->drm, i);
579 					drm_dbg_kms(&dev_priv->drm,
590 			if (drm_WARN_ON(&dev_priv->drm,
656 static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
661 	intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
674 		intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
678 	intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
694 static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
701 		glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
711 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
729 	if (drm_WARN_ON(&dev_priv->drm,
748 	skl_scaler_setup_filter(dev_priv, pipe, id, 0,
751 	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
753 	intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
755 	intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
757 	intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
759 	intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
768 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
792 	    !icl_is_hdr_plane(dev_priv, plane->id)) {
811 	skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
814 	intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
815 	intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
817 	intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
819 	intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
821 	intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
828 	struct drm_i915_private *dev_priv = to_i915(dev);
830 	intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
831 	intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
832 	intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
864 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
873 		ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
880 		pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
881 		size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));