i915/display/intel_vdsc.c

265 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
278 		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
289 	if (DISPLAY_VER(dev_priv) >= 14 &&
316 	if (DISPLAY_VER(dev_priv) >= 13) {
429 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
460 	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
465 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
471 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
477 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
483 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
489 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
497 	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
503 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
509 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
515 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
523 	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
532 	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
535 	if (DISPLAY_VER(dev_priv) >= 14) {
538 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
544 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
554 		drm_dbg_kms(&dev_priv->drm, "RC_BUF_THRESH_%d = 0x%08x\n", i,
558 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0,
560 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW,
562 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1,
564 		intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW,
567 			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0,
569 			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW,
571 			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1,
573 			intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW,
577 		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe),
579 		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
581 		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe),
583 		intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
586 			intel_de_write(dev_priv,
589 			intel_de_write(dev_priv,
592 			intel_de_write(dev_priv,
595 			intel_de_write(dev_priv,
611 		drm_dbg_kms(&dev_priv->drm, "RC_RANGE_PARAM_%d = 0x%08x\n", i,
615 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0,
617 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW,
619 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1,
621 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW,
623 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2,
625 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW,
627 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3,
629 		intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW,
632 			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0,
634 			intel_de_write(dev_priv,
637 			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1,
639 			intel_de_write(dev_priv,
642 			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2,
644 			intel_de_write(dev_priv,
647 			intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3,
649 			intel_de_write(dev_priv,
654 		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
656 		intel_de_write(dev_priv,
659 		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
661 		intel_de_write(dev_priv,
664 		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
666 		intel_de_write(dev_priv,
669 		intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
671 		intel_de_write(dev_priv,
675 			intel_de_write(dev_priv,
678 			intel_de_write(dev_priv,
681 			intel_de_write(dev_priv,
684 			intel_de_write(dev_priv,
687 			intel_de_write(dev_priv,
690 			intel_de_write(dev_priv,
693 			intel_de_write(dev_priv,
696 			intel_de_write(dev_priv,
761 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
770 		intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
777 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
797 	intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
798 	intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
804 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
809 		intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
810 		intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
964 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
975 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
979 	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
980 	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));
991 	intel_display_power_put(dev_priv, power_domain, wakeref);