i915/display/intel_sprite.c

71 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
104 	intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id),
106 	intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id),
108 	intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id),
111 	intel_de_write_fw(dev_priv, SPCSCC01(plane_id),
113 	intel_de_write_fw(dev_priv, SPCSCC23(plane_id),
115 	intel_de_write_fw(dev_priv, SPCSCC45(plane_id),
117 	intel_de_write_fw(dev_priv, SPCSCC67(plane_id),
119 	intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8]));
121 	intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id),
123 	intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id),
125 	intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id),
128 	intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id),
130 	intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id),
132 	intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id),
143 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
172 	intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id),
174 	intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id),
346 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
362 		intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1),
371 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
379 	intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
381 	intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
383 	intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
392 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
405 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
409 		intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
411 		intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id),
413 		intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id),
417 	intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
419 	intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
420 	intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
428 	intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl);
429 	intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
440 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
444 	intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
445 	intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
452 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
459 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
463 	ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
467 	intel_display_power_put(dev_priv, power_domain, wakeref);
645 	struct drm_i915_private *dev_priv =
650 		(IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv));
656 	struct drm_i915_private *dev_priv =
665 	if (IS_IVYBRIDGE(dev_priv))
755 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
767 		intel_de_write_fw(dev_priv, SPRGAMC(pipe, i),
770 	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]);
771 	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]);
772 	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]);
775 	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]);
776 	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]);
777 	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]);
786 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
801 	intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
803 	intel_de_write_fw(dev_priv, SPRPOS(pipe),
805 	intel_de_write_fw(dev_priv, SPRSIZE(pipe),
807 	if (IS_IVYBRIDGE(dev_priv))
808 		intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
816 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
829 		intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
830 		intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
832 		intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value);
837 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
838 		intel_de_write_fw(dev_priv, SPROFFSET(pipe),
841 		intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
842 		intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
851 	intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl);
852 	intel_de_write_fw(dev_priv, SPRSURF(pipe),
862 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
865 	intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
867 	if (IS_IVYBRIDGE(dev_priv))
868 		intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);
869 	intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);
876 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
882 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
886 	ret =  intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
890 	intel_display_power_put(dev_priv, power_domain, wakeref);
984 	struct drm_i915_private *dev_priv =
993 	if (IS_SANDYBRIDGE(dev_priv))
1055 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1070 		intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1),
1085 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1099 		intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i),
1102 	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
1103 	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
1104 	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
1113 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1128 	intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
1130 	intel_de_write_fw(dev_priv, DVSPOS(pipe),
1132 	intel_de_write_fw(dev_priv, DVSSIZE(pipe),
1134 	intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
1142 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1155 		intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
1156 		intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
1158 		intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value);
1161 	intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset);
1162 	intel_de_write_fw(dev_priv, DVSTILEOFF(pipe),
1170 	intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr);
1171 	intel_de_write_fw(dev_priv, DVSSURF(pipe),
1174 	if (IS_G4X(dev_priv))
1184 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1187 	intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);
1189 	intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);
1190 	intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);
1197 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1203 	wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1207 	ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE;
1211 	intel_display_power_put(dev_priv, power_domain, wakeref);
1300 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1306 		if (DISPLAY_VER(dev_priv) < 7) {
1309 		} else if (IS_IVYBRIDGE(dev_priv)) {
1335 	if (DISPLAY_VER(dev_priv) >= 7)
1346 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1350 	if (IS_CHERRYVIEW(dev_priv) &&
1353 		drm_dbg_kms(&dev_priv->drm,
1552 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1567 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1576 		if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1585 	} else if (DISPLAY_VER(dev_priv) >= 7) {
1592 		if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
1613 		if (IS_SANDYBRIDGE(dev_priv)) {
1626 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1639 	modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X);
1641 	ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
1645 				       "sprite %c", sprite_name(dev_priv, pipe, sprite));