i915/display/intel_sprite.c

52 static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite)
54 	return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A';
145 	enum pipe pipe = plane->pipe;
172 	intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id),
174 	intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id),
348 	enum pipe pipe = plane->pipe;
362 		intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1),
372 	enum pipe pipe = plane->pipe;
379 	intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
381 	intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
383 	intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
393 	enum pipe pipe = plane->pipe;
405 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
409 		intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id),
411 		intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id),
413 		intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id),
417 	intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
419 	intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
420 	intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
428 	intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl);
429 	intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id),
441 	enum pipe pipe = plane->pipe;
444 	intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
445 	intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
450 			enum pipe *pipe)
458 	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
463 	ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE;
465 	*pipe = plane->pipe;
737 	 *  correction, pipe gamma correction, or pipe color space
756 	enum pipe pipe = plane->pipe;
767 		intel_de_write_fw(dev_priv, SPRGAMC(pipe, i),
770 	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]);
771 	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]);
772 	intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]);
775 	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]);
776 	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]);
777 	intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]);
787 	enum pipe pipe = plane->pipe;
801 	intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
803 	intel_de_write_fw(dev_priv, SPRPOS(pipe),
805 	intel_de_write_fw(dev_priv, SPRSIZE(pipe),
808 		intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
817 	enum pipe pipe = plane->pipe;
829 		intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
830 		intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
832 		intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value);
838 		intel_de_write_fw(dev_priv, SPROFFSET(pipe),
841 		intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
842 		intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
851 	intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl);
852 	intel_de_write_fw(dev_priv, SPRSURF(pipe),
863 	enum pipe pipe = plane->pipe;
865 	intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
868 		intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);
869 	intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);
874 			enum pipe *pipe)
881 	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
886 	ret =  intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE;
888 	*pipe = plane->pipe;
933 	 * on the other pipe, but we can't really check for that,
1057 	enum pipe pipe = plane->pipe;
1070 		intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1),
1087 	enum pipe pipe = plane->pipe;
1099 		intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i),
1102 	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
1103 	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
1104 	intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
1114 	enum pipe pipe = plane->pipe;
1128 	intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
1130 	intel_de_write_fw(dev_priv, DVSPOS(pipe),
1132 	intel_de_write_fw(dev_priv, DVSSIZE(pipe),
1134 	intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
1143 	enum pipe pipe = plane->pipe;
1155 		intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
1156 		intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
1158 		intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value);
1161 	intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset);
1162 	intel_de_write_fw(dev_priv, DVSTILEOFF(pipe),
1170 	intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr);
1171 	intel_de_write_fw(dev_priv, DVSSURF(pipe),
1185 	enum pipe pipe = plane->pipe;
1187 	intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);
1189 	intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);
1190 	intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);
1195 			enum pipe *pipe)
1202 	power_domain = POWER_DOMAIN_PIPE(plane->pipe);
1207 	ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE;
1209 	*pipe = plane->pipe;
1553 			  enum pipe pipe, int sprite)
1576 		if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1626 	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1635 	plane->pipe = pipe;
1637 	plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
1645 				       "sprite %c", sprite_name(dev_priv, pipe, sprite));