i915/display/intel_sdvo.c

216 	struct drm_i915_private *dev_priv = to_i915(dev);
220 	if (HAS_PCH_SPLIT(dev_priv)) {
221 		intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
222 		intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
227 		if (HAS_PCH_IBX(dev_priv)) {
228 			intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
229 			intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
235 		cval = intel_de_read(dev_priv, GEN3_SDVOC);
237 		bval = intel_de_read(dev_priv, GEN3_SDVOB);
245 		intel_de_write(dev_priv, GEN3_SDVOB, bval);
246 		intel_de_posting_read(dev_priv, GEN3_SDVOB);
248 		intel_de_write(dev_priv, GEN3_SDVOC, cval);
249 		intel_de_posting_read(dev_priv, GEN3_SDVOC);
417 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
438 	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
441 	drm_dbg_kms(&dev_priv->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo),
542 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
607 	drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
610 	drm_dbg_kms(&dev_priv->drm, "%s: R: %s\n",
615 	drm_dbg_kms(&dev_priv->drm, "%s: R: ... failed %s\n",
1102 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1128 	if (drm_WARN_ON(&dev_priv->drm, ret))
1137 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1146 	if (drm_WARN_ON(&dev_priv->drm,
1151 	if (drm_WARN_ON(&dev_priv->drm, len < 0))
1284 	struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1305 		drm_dbg_kms(&dev_priv->drm,
1527 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1572 		drm_info(&dev_priv->drm,
1602 		drm_info(&dev_priv->drm,
1608 		drm_WARN(&dev_priv->drm, 1,
1619 	if (DISPLAY_VER(dev_priv) >= 4) {
1623 		if (DISPLAY_VER(dev_priv) < 5)
1626 		sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1634 	if (HAS_PCH_CPT(dev_priv))
1639 	if (DISPLAY_VER(dev_priv) >= 4) {
1641 	} else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1642 		   IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1650 	    DISPLAY_VER(dev_priv) < 5)
1667 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1672 	val = intel_de_read(dev_priv, sdvo_reg);
1675 	if (HAS_PCH_CPT(dev_priv))
1677 	else if (IS_CHERRYVIEW(dev_priv))
1688 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1695 	ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1704 	struct drm_i915_private *dev_priv = to_i915(dev);
1715 	sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1723 		drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
1746 	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1840 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1850 	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1860 	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1865 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1866 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1875 		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1876 		intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1877 		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1902 	struct drm_i915_private *dev_priv = to_i915(dev);
1912 	temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1927 		drm_dbg_kms(&dev_priv->drm,
2032 	struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
2035 	if (!I915_HAS_HOTPLUG(dev_priv))
2042 	if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2351 	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2353 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2617 	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2622 		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2624 		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2640 	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2645 		mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2647 		mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2650 	    intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2655 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n",
2659 	sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2685 	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2689 		my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2690 		other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2692 		my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2693 		other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
3348 	struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
3349 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
3365 static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port)
3367 	if (HAS_PCH_SPLIT(dev_priv))
3373 static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
3376 	return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port),
3380 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3387 	if (!assert_port_valid(dev_priv, port))
3390 	if (!assert_sdvo_port_valid(dev_priv, port))
3403 	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3417 			drm_dbg_kms(&dev_priv->drm,
3425 	if (HAS_PCH_SPLIT(dev_priv)) {
3455 		drm_dbg_kms(&dev_priv->drm,
3492 	drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "