Lines Matching refs:intel_dp
35 #include "intel_dp.h"
192 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
193 (intel_dp)->psr.source_support)
204 static bool psr_global_enabled(struct intel_dp *intel_dp)
206 struct intel_connector *connector = intel_dp->attached_connector;
207 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
209 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
221 static bool psr2_global_enabled(struct intel_dp *intel_dp)
223 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
225 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
236 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
238 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
241 EDP_PSR_ERROR(intel_dp->psr.transcoder);
244 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)
246 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
249 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
252 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)
254 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
257 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
260 static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
262 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
265 EDP_PSR_MASK(intel_dp->psr.transcoder);
340 static void psr_irq_control(struct intel_dp *intel_dp)
342 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
343 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
346 if (intel_dp->psr.panel_replay_enabled)
349 mask = psr_irq_psr_error_bit_get(intel_dp);
350 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
351 mask |= psr_irq_post_exit_bit_get(intel_dp) |
352 psr_irq_pre_entry_bit_get(intel_dp);
355 psr_irq_mask_get(intel_dp), ~mask);
396 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
398 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
399 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
402 if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {
403 intel_dp->psr.last_entry_attempt = time_ns;
409 if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {
410 intel_dp->psr.last_exit = time_ns;
420 psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
424 if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {
428 intel_dp->psr.irq_aux_error = true;
439 0, psr_irq_psr_error_bit_get(intel_dp));
441 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
445 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
449 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
455 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
457 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
460 if (drm_dp_dpcd_readb(&intel_dp->aux,
469 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
471 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
477 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
484 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
495 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
505 intel_dp->psr.su_w_granularity = w;
506 intel_dp->psr.su_y_granularity = y;
509 static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
511 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
514 intel_dp->psr.sink_panel_replay_support = false;
515 drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
525 intel_dp->psr.sink_panel_replay_support = true;
528 static void _psr_init_dpcd(struct intel_dp *intel_dp)
531 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
534 intel_dp->psr_dpcd[0]);
536 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
542 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
548 intel_dp->psr.sink_support = true;
549 intel_dp->psr.sink_sync_latency =
550 intel_dp_get_sink_sync_latency(intel_dp);
553 intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
554 bool y_req = intel_dp->psr_dpcd[1] &
556 bool alpm = intel_dp_get_alpm_status(intel_dp);
569 intel_dp->psr.sink_psr2_support = y_req && alpm;
571 intel_dp->psr.sink_psr2_support ? "" : "not ");
575 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
577 _panel_replay_init_dpcd(intel_dp);
579 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
580 sizeof(intel_dp->psr_dpcd));
582 if (intel_dp->psr_dpcd[0])
583 _psr_init_dpcd(intel_dp);
585 if (intel_dp->psr.sink_psr2_support)
586 intel_dp_get_su_granularity(intel_dp);
589 static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
591 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
592 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
610 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
613 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg),
626 static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
628 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
631 intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
632 !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
638 static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp)
640 return intel_dp->psr.panel_replay_enabled ?
648 void intel_psr_enable_sink(struct intel_dp *intel_dp,
651 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
657 drm_dp_dpcd_writeb(&intel_dp->aux,
662 if (psr2_su_region_et_valid(intel_dp))
668 if (intel_dp->psr.link_standby)
682 if (intel_dp->psr.entry_setup_frames > 0)
685 drm_dp_dpcd_writeb(&intel_dp->aux,
686 intel_psr_get_enable_sink_offset(intel_dp),
689 if (intel_dp_is_edp(intel_dp))
690 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
693 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
695 struct intel_connector *connector = intel_dp->attached_connector;
696 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
737 drm_dp_tps3_supported(intel_dp->dpcd))
745 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
747 struct intel_connector *connector = intel_dp->attached_connector;
748 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
755 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
763 static void hsw_activate_psr1(struct intel_dp *intel_dp)
765 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
766 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
770 val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
778 if (intel_dp->psr.link_standby)
781 val |= intel_psr1_get_tp_time(intel_dp);
787 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
793 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
795 struct intel_connector *connector = intel_dp->attached_connector;
796 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
815 static int psr2_block_count_lines(struct intel_dp *intel_dp)
817 return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&
818 intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
821 static int psr2_block_count(struct intel_dp *intel_dp)
823 return psr2_block_count_lines(intel_dp) / 4;
826 static u8 frames_before_su_entry(struct intel_dp *intel_dp)
831 intel_dp->psr.sink_sync_latency + 1,
835 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
836 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
841 static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
843 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
845 intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
848 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
852 static void hsw_activate_psr2(struct intel_dp *intel_dp)
854 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
855 struct intel_psr *psr = &intel_dp->psr;
856 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
860 val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
868 val |= EDP_PSR2_FRAME_BEFORE_SU(frames_before_su_entry(intel_dp));
870 val |= intel_psr2_get_tp_time(intel_dp);
873 if (psr2_block_count(intel_dp) > 2)
911 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
915 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
917 if (intel_dp->psr.psr2_sel_fetch_enabled) {
926 if (psr2_su_region_et_valid(intel_dp))
960 static void psr2_program_idle_frames(struct intel_dp *intel_dp,
963 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
964 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
971 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
973 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
975 psr2_program_idle_frames(intel_dp, 0);
979 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
981 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
984 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
989 struct intel_dp *intel_dp =
990 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
992 mutex_lock(&intel_dp->psr.lock);
994 if (delayed_work_pending(&intel_dp->psr.dc3co_work))
997 tgl_psr2_disable_dc3co(intel_dp);
999 mutex_unlock(&intel_dp->psr.lock);
1002 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
1004 if (!intel_dp->psr.dc3co_exitline)
1007 cancel_delayed_work(&intel_dp->psr.dc3co_work);
1009 tgl_psr2_disable_dc3co(intel_dp);
1013 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
1016 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1018 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1028 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
1032 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1053 if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
1073 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
1076 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1079 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
1091 if (psr2_su_region_et_valid(intel_dp))
1097 static bool psr2_granularity_check(struct intel_dp *intel_dp,
1100 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1107 if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
1110 if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
1115 return intel_dp->psr.su_y_granularity == 4;
1123 y_granularity = intel_dp->psr.su_y_granularity;
1124 else if (intel_dp->psr.su_y_granularity <= 2)
1126 else if ((intel_dp->psr.su_y_granularity % 4) == 0)
1127 y_granularity = intel_dp->psr.su_y_granularity;
1140 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
1144 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1157 if (DISPLAY_VER(dev_priv) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
1267 static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
1270 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1292 intel_dp->psr.alpm_parameters.fast_wake_lines = aux_less_wake_lines;
1293 intel_dp->psr.alpm_parameters.silence_period_sym_clocks = silence_period;
1294 intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
1299 static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
1302 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1315 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
1321 intel_dp->psr.alpm_parameters.check_entry_lines = check_entry_lines;
1351 static bool _compute_alpm_params(struct intel_dp *intel_dp,
1354 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1382 if (!_lnl_compute_alpm_params(intel_dp, crtc_state))
1389 intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
1390 intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
1395 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
1398 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1399 int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
1405 intel_dp->psr_dpcd[1]);
1428 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
1431 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1436 if (!intel_dp->psr.sink_psr2_support)
1464 if (!psr2_global_enabled(intel_dp)) {
1516 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
1522 if (!_compute_alpm_params(intel_dp, crtc_state)) {
1531 psr2_block_count_lines(intel_dp)) {
1538 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
1546 if (!psr2_granularity_check(intel_dp, crtc_state)) {
1560 tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
1568 static bool _psr_compute_config(struct intel_dp *intel_dp,
1571 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1582 if (!CAN_PSR(intel_dp))
1585 entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode);
1588 intel_dp->psr.entry_setup_frames = entry_setup_frames;
1598 void intel_psr_compute_config(struct intel_dp *intel_dp,
1602 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1605 if (!psr_global_enabled(intel_dp)) {
1610 if (intel_dp->psr.sink_not_reliable) {
1633 if (CAN_PANEL_REPLAY(intel_dp))
1637 _psr_compute_config(intel_dp, crtc_state);
1642 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
1651 struct intel_dp *intel_dp;
1657 intel_dp = &dig_port->dp;
1658 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
1661 mutex_lock(&intel_dp->psr.lock);
1662 if (!intel_dp->psr.enabled)
1665 if (intel_dp->psr.panel_replay_enabled) {
1675 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1678 if (!intel_dp->psr.psr2_enabled)
1692 mutex_unlock(&intel_dp->psr.lock);
1695 static void intel_psr_activate(struct intel_dp *intel_dp)
1697 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1698 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1707 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1709 lockdep_assert_held(&intel_dp->psr.lock);
1712 if (intel_dp->psr.panel_replay_enabled)
1713 dg2_activate_panel_replay(intel_dp);
1714 else if (intel_dp->psr.psr2_enabled)
1715 hsw_activate_psr2(intel_dp);
1717 hsw_activate_psr1(intel_dp);
1719 intel_dp->psr.active = true;
1722 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
1724 switch (intel_dp->psr.pipe) {
1734 MISSING_CASE(intel_dp->psr.pipe);
1743 static void wm_optimization_wa(struct intel_dp *intel_dp,
1746 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1760 0, wa_16013835468_bit_get(intel_dp));
1763 wa_16013835468_bit_get(intel_dp), 0);
1766 static void lnl_alpm_configure(struct intel_dp *intel_dp)
1768 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1769 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1770 struct intel_psr *psr = &intel_dp->psr;
1773 if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled &&
1774 !intel_dp_is_edp(intel_dp)))
1781 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
1811 static void intel_psr_enable_source(struct intel_dp *intel_dp,
1814 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1815 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1823 hsw_psr_setup_aux(intel_dp);
1839 if (DISPLAY_VER(dev_priv) < 20 || intel_dp_is_edp(intel_dp))
1842 if (intel_dp_is_edp(intel_dp)) {
1873 psr_irq_control(intel_dp);
1879 if (intel_dp->psr.dc3co_exitline)
1881 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
1885 intel_dp->psr.psr2_sel_fetch_enabled ?
1888 if (intel_dp_is_edp(intel_dp))
1889 lnl_alpm_configure(intel_dp);
1895 wm_optimization_wa(intel_dp, crtc_state);
1897 if (intel_dp->psr.psr2_enabled) {
1924 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1926 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1927 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1930 if (intel_dp->psr.panel_replay_enabled)
1942 val &= psr_irq_psr_error_bit_get(intel_dp);
1944 intel_dp->psr.sink_not_reliable = true;
1954 static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1957 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1958 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1961 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1963 intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1964 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
1965 intel_dp->psr.busy_frontbuffer_bits = 0;
1966 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1967 intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1970 intel_dp->psr.dc3co_exit_delay = val;
1971 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1972 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1973 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1974 intel_dp->psr.req_psr2_sdp_prior_scanline =
1977 if (!psr_interrupt_error_check(intel_dp))
1980 if (intel_dp->psr.panel_replay_enabled) {
1984 intel_dp->psr.psr2_enabled ? "2" : "1");
1990 intel_psr_enable_sink(intel_dp, crtc_state);
1993 if (intel_dp_is_edp(intel_dp))
1996 intel_psr_enable_source(intel_dp, crtc_state);
1997 intel_dp->psr.enabled = true;
1998 intel_dp->psr.paused = false;
2000 intel_psr_activate(intel_dp);
2003 static void intel_psr_exit(struct intel_dp *intel_dp)
2005 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2006 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2009 if (!intel_dp->psr.active) {
2021 if (intel_dp->psr.panel_replay_enabled) {
2022 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
2024 } else if (intel_dp->psr.psr2_enabled) {
2025 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
2037 intel_dp->psr.active = false;
2040 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
2042 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2043 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2047 if (intel_dp->psr.psr2_enabled) {
2061 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
2063 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2064 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2066 lockdep_assert_held(&intel_dp->psr.lock);
2068 if (!intel_dp->psr.enabled)
2071 if (intel_dp->psr.panel_replay_enabled)
2075 intel_dp->psr.psr2_enabled ? "2" : "1");
2077 intel_psr_exit(intel_dp);
2078 intel_psr_wait_exit_locked(intel_dp);
2086 wa_16013835468_bit_get(intel_dp), 0);
2088 if (intel_dp->psr.psr2_enabled) {
2099 if (intel_dp_is_edp(intel_dp))
2100 intel_snps_phy_update_psr_power_state(&dp_to_dig_port(intel_dp)->base, false);
2103 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
2113 drm_dp_dpcd_writeb(&intel_dp->aux,
2114 intel_psr_get_enable_sink_offset(intel_dp), 0);
2116 if (!intel_dp->psr.panel_replay_enabled &&
2117 intel_dp->psr.psr2_enabled)
2118 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
2120 intel_dp->psr.enabled = false;
2121 intel_dp->psr.panel_replay_enabled = false;
2122 intel_dp->psr.psr2_enabled = false;
2123 intel_dp->psr.psr2_sel_fetch_enabled = false;
2124 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2129 * @intel_dp: Intel DP
2134 void intel_psr_disable(struct intel_dp *intel_dp,
2137 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2142 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
2145 mutex_lock(&intel_dp->psr.lock);
2147 intel_psr_disable_locked(intel_dp);
2149 mutex_unlock(&intel_dp->psr.lock);
2150 cancel_work_sync(&intel_dp->psr.work);
2151 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
2156 * @intel_dp: Intel DP
2160 void intel_psr_pause(struct intel_dp *intel_dp)
2162 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2163 struct intel_psr *psr = &intel_dp->psr;
2165 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
2178 intel_psr_exit(intel_dp);
2179 intel_psr_wait_exit_locked(intel_dp);
2190 * @intel_dp: Intel DP
2194 void intel_psr_resume(struct intel_dp *intel_dp)
2196 struct intel_psr *psr = &intel_dp->psr;
2198 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
2207 intel_psr_activate(intel_dp);
2240 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
2242 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2243 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2245 if (intel_dp->psr.psr2_sel_fetch_enabled)
2266 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2281 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2283 lockdep_assert_held(&intel_dp->psr.lock);
2284 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
2675 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2676 struct intel_psr *psr = &intel_dp->psr;
2696 intel_psr_disable_locked(intel_dp);
2699 wm_optimization_wa(intel_dp, new_crtc_state);
2718 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2719 struct intel_psr *psr = &intel_dp->psr;
2734 intel_psr_enable_locked(intel_dp, crtc_state);
2737 wm_optimization_wa(intel_dp, crtc_state);
2741 psr_force_hw_tracking_exit(intel_dp);
2747 intel_dp->psr.busy_frontbuffer_bits = 0;
2753 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
2755 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2756 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2768 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
2770 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2771 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2801 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2804 lockdep_assert_held(&intel_dp->psr.lock);
2806 if (!intel_dp->psr.enabled)
2809 if (intel_dp->psr.psr2_enabled)
2810 ret = _psr2_ready_for_pipe_update_locked(intel_dp);
2812 ret = _psr1_ready_for_pipe_update_locked(intel_dp);
2819 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
2821 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2822 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2827 if (!intel_dp->psr.enabled)
2830 if (intel_dp->psr.psr2_enabled) {
2838 mutex_unlock(&intel_dp->psr.lock);
2846 mutex_lock(&intel_dp->psr.lock);
2847 return err == 0 && intel_dp->psr.enabled;
2913 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
2915 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2926 ret = mutex_lock_interruptible(&intel_dp->psr.lock);
2930 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
2931 intel_dp->psr.debug = val;
2937 if (intel_dp->psr.enabled)
2938 psr_irq_control(intel_dp);
2940 mutex_unlock(&intel_dp->psr.lock);
2948 static void intel_psr_handle_irq(struct intel_dp *intel_dp)
2950 struct intel_psr *psr = &intel_dp->psr;
2952 intel_psr_disable_locked(intel_dp);
2955 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
2960 struct intel_dp *intel_dp =
2961 container_of(work, typeof(*intel_dp), psr.work);
2963 mutex_lock(&intel_dp->psr.lock);
2965 if (!intel_dp->psr.enabled)
2968 if (READ_ONCE(intel_dp->psr.irq_aux_error))
2969 intel_psr_handle_irq(intel_dp);
2977 if (!__psr_wait_for_idle_locked(intel_dp))
2985 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2988 intel_psr_activate(intel_dp);
2990 mutex_unlock(&intel_dp->psr.lock);
2993 static void _psr_invalidate_handle(struct intel_dp *intel_dp)
2995 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2996 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2998 if (intel_dp->psr.psr2_sel_fetch_enabled) {
3001 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3003 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3011 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3012 intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
3014 intel_psr_exit(intel_dp);
3041 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3043 mutex_lock(&intel_dp->psr.lock);
3044 if (!intel_dp->psr.enabled) {
3045 mutex_unlock(&intel_dp->psr.lock);
3050 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3051 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
3054 _psr_invalidate_handle(intel_dp);
3056 mutex_unlock(&intel_dp->psr.lock);
3066 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
3069 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3071 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
3072 !intel_dp->psr.active)
3080 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
3083 tgl_psr2_enable_dc3co(intel_dp);
3084 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work,
3085 intel_dp->psr.dc3co_exit_delay);
3088 static void _psr_flush_handle(struct intel_dp *intel_dp)
3090 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3091 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3093 if (intel_dp->psr.psr2_sel_fetch_enabled) {
3094 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3096 if (intel_dp->psr.busy_frontbuffer_bits == 0) {
3110 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3111 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
3118 psr_force_hw_tracking_exit(intel_dp);
3121 psr_force_hw_tracking_exit(intel_dp);
3123 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
3124 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
3148 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3150 mutex_lock(&intel_dp->psr.lock);
3151 if (!intel_dp->psr.enabled) {
3152 mutex_unlock(&intel_dp->psr.lock);
3157 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3158 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
3165 if (intel_dp->psr.paused)
3170 !intel_dp->psr.psr2_sel_fetch_enabled)) {
3171 tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
3179 _psr_flush_handle(intel_dp);
3181 mutex_unlock(&intel_dp->psr.lock);
3187 * @intel_dp: Intel DP
3193 void intel_psr_init(struct intel_dp *intel_dp)
3195 struct intel_connector *connector = intel_dp->attached_connector;
3196 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3197 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3217 if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp))
3218 intel_dp->psr.source_panel_replay_support = true;
3220 intel_dp->psr.source_support = true;
3223 intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
3228 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
3230 INIT_WORK(&intel_dp->psr.work, intel_psr_work);
3231 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
3232 mutex_init(&intel_dp->psr.lock);
3235 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
3238 struct drm_dp_aux *aux = &intel_dp->aux;
3242 offset = intel_dp->psr.panel_replay_enabled ?
3249 offset = intel_dp->psr.panel_replay_enabled ?
3261 static void psr_alpm_check(struct intel_dp *intel_dp)
3263 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3264 struct drm_dp_aux *aux = &intel_dp->aux;
3265 struct intel_psr *psr = &intel_dp->psr;
3279 intel_psr_disable_locked(intel_dp);
3289 static void psr_capability_changed_check(struct intel_dp *intel_dp)
3291 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3292 struct intel_psr *psr = &intel_dp->psr;
3296 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
3303 intel_psr_disable_locked(intel_dp);
3309 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
3320 void intel_psr_short_pulse(struct intel_dp *intel_dp)
3322 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3323 struct intel_psr *psr = &intel_dp->psr;
3329 if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
3337 if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
3345 intel_psr_disable_locked(intel_dp);
3368 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
3371 psr_alpm_check(intel_dp);
3372 psr_capability_changed_check(intel_dp);
3379 bool intel_psr_enabled(struct intel_dp *intel_dp)
3383 if (!CAN_PSR(intel_dp))
3386 mutex_lock(&intel_dp->psr.lock);
3387 ret = intel_dp->psr.enabled;
3388 mutex_unlock(&intel_dp->psr.lock);
3411 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3413 mutex_lock(&intel_dp->psr.lock);
3434 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3436 mutex_unlock(&intel_dp->psr.lock);
3442 psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
3444 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3445 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3449 if (intel_dp->psr.psr2_enabled) {
3487 static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
3489 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3490 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3491 struct intel_psr *psr = &intel_dp->psr;
3501 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
3537 psr_source_status(intel_dp, m);
3592 struct intel_dp *intel_dp = NULL;
3600 intel_dp = enc_to_intel_dp(encoder);
3604 if (!intel_dp)
3607 return intel_psr_status(m, intel_dp);
3623 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3630 ret = intel_psr_debug_set(intel_dp, val);
3648 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3651 *val = READ_ONCE(intel_dp->psr.debug);
3673 static const char *psr_mode_str(struct intel_dp *intel_dp)
3675 if (intel_dp->psr.panel_replay_enabled)
3677 else if (intel_dp->psr.enabled)
3686 struct intel_dp *intel_dp = intel_attached_dp(connector);
3708 if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {
3716 ret = psr_get_status_and_error_status(intel_dp, &status, &error_status);
3721 if (intel_dp->psr.panel_replay_enabled) {
3725 } else if (intel_dp->psr.enabled) {
3731 seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str);
3733 seq_printf(m, "Sink %s error status: 0x%x", psr_mode_str(intel_dp), error_status);
3742 seq_printf(m, "\t%s RFB storage error\n", psr_mode_str(intel_dp));
3744 seq_printf(m, "\t%s VSC SDP uncorrectable error\n", psr_mode_str(intel_dp));
3746 seq_printf(m, "\t%s Link CRC error\n", psr_mode_str(intel_dp));
3755 struct intel_dp *intel_dp = intel_attached_dp(connector);
3757 return intel_psr_status(m, intel_dp);