i915/display/intel_psr.c

238 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
240 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR :
246 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
248 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT :
254 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
256 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY :
262 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
264 	return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK :
268 static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv,
271 	if (DISPLAY_VER(dev_priv) >= 8)
277 static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv,
280 	if (DISPLAY_VER(dev_priv) >= 8)
286 static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv,
289 	if (DISPLAY_VER(dev_priv) >= 8)
295 static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv,
298 	if (DISPLAY_VER(dev_priv) >= 8)
304 static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv,
307 	if (DISPLAY_VER(dev_priv) >= 12)
313 static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv,
316 	if (DISPLAY_VER(dev_priv) >= 12)
322 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv,
325 	if (DISPLAY_VER(dev_priv) >= 8)
331 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv,
334 	if (DISPLAY_VER(dev_priv) >= 8)
342 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
354 	intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder),
398 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
404 		drm_dbg_kms(&dev_priv->drm,
411 		drm_dbg_kms(&dev_priv->drm,
415 		if (DISPLAY_VER(dev_priv) >= 9) {
418 			val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
420 			psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
425 		drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
438 		intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder),
441 		queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
591 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
606 		intel_de_write(dev_priv,
607 			       psr_aux_data_reg(dev_priv, cpu_transcoder, i >> 2),
622 	intel_de_write(dev_priv, psr_aux_ctl_reg(dev_priv, cpu_transcoder),
651 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
671 		if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8)
696 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
699 	if (DISPLAY_VER(dev_priv) >= 11)
702 	if (dev_priv->display.params.psr_safest_params) {
730 	if (DISPLAY_VER(dev_priv) < 9 &&
736 	if (intel_dp_source_supports_tps3(dev_priv) &&
748 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
757 	if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
765 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
772 	if (DISPLAY_VER(dev_priv) < 20)
775 	if (IS_HASWELL(dev_priv))
783 	if (DISPLAY_VER(dev_priv) >= 8)
786 	if (DISPLAY_VER(dev_priv) >= 20)
789 	intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder),
796 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
799 	if (dev_priv->display.params.psr_safest_params)
843 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
845 	intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
848 	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
854 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
862 	if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
865 	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) < 13)
872 	if (DISPLAY_VER(dev_priv) >= 12) {
880 	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
903 	} else if (DISPLAY_VER(dev_priv) >= 12) {
906 	} else if (DISPLAY_VER(dev_priv) >= 9) {
914 	if (DISPLAY_VER(dev_priv) >= 20)
920 		tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
921 		drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
922 	} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
923 		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
933 	intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val);
935 	intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val);
939 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder)
941 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
943 	else if (DISPLAY_VER(dev_priv) >= 12)
945 	else if (DISPLAY_VER(dev_priv) >= 9)
963 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
966 	intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
973 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
976 	intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
981 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
983 	intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
1018 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1021 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
1032 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1033 	struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
1057 	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1067 	if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
1076 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1078 	if (!dev_priv->display.params.enable_psr2_sel_fetch &&
1080 		drm_dbg_kms(&dev_priv->drm,
1086 		drm_dbg_kms(&dev_priv->drm,
1100 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1122 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
1144 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1157 	if (DISPLAY_VER(dev_priv) < 14 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
1431 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1440 	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
1441 		drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
1446 	if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
1447 	    IS_DG2(dev_priv)) {
1448 		drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
1452 	if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
1453 		drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
1457 	if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
1458 		drm_dbg_kms(&dev_priv->drm,
1465 		drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
1475 	    (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))) {
1476 		drm_dbg_kms(&dev_priv->drm,
1482 		drm_dbg_kms(&dev_priv->drm,
1487 	if (DISPLAY_VER(dev_priv) >= 12) {
1491 	} else if (DISPLAY_VER(dev_priv) >= 10) {
1495 	} else if (DISPLAY_VER(dev_priv) == 9) {
1502 		drm_dbg_kms(&dev_priv->drm,
1510 	    IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
1511 		drm_dbg_kms(&dev_priv->drm,
1517 		drm_dbg_kms(&dev_priv->drm,
1523 		drm_dbg_kms(&dev_priv->drm,
1532 		drm_dbg_kms(&dev_priv->drm,
1537 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1539 		    !HAS_PSR_HW_TRACKING(dev_priv)) {
1540 			drm_dbg_kms(&dev_priv->drm,
1547 		drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
1553 		drm_dbg_kms(&dev_priv->drm,
1571 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1590 		drm_dbg_kms(&dev_priv->drm,
1602 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1606 		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
1611 		drm_dbg_kms(&dev_priv->drm,
1617 		drm_dbg_kms(&dev_priv->drm,
1628 		drm_dbg_kms(&dev_priv->drm,
1648 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1681 	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1682 		val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder));
1687 	if (DISPLAY_VER(dev_priv) >= 12) {
1688 		val = intel_de_read(dev_priv, TRANS_EXITLINE(cpu_transcoder));
1697 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1700 	drm_WARN_ON(&dev_priv->drm,
1701 		    transcoder_has_psr2(dev_priv, cpu_transcoder) &&
1702 		    intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE);
1704 	drm_WARN_ON(&dev_priv->drm,
1705 		    intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE);
1707 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1746 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1750 	if (IS_DISPLAY_VER(dev_priv, 11, 14))
1754 	if (DISPLAY_VER(dev_priv) == 12)
1759 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
1762 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
1768 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1773 	if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled &&
1786 		intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
1793 		intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder),
1808 	intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
1814 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1822 	if (DISPLAY_VER(dev_priv) < 9)
1839 	if (DISPLAY_VER(dev_priv) < 20 || intel_dp_is_edp(intel_dp))
1853 		if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL_ULT(dev_priv))
1856 		if (DISPLAY_VER(dev_priv) < 20)
1863 		if (IS_DISPLAY_VER(dev_priv, 9, 10))
1867 		if (IS_HASWELL(dev_priv))
1871 	intel_de_write(dev_priv, psr_debug_reg(dev_priv, cpu_transcoder), mask);
1880 		intel_de_rmw(dev_priv, TRANS_EXITLINE(cpu_transcoder), EXITLINE_MASK,
1883 	if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1884 		intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1898 		if (DISPLAY_VER(dev_priv) == 9)
1899 			intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1908 		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
1909 		    IS_ALDERLAKE_P(dev_priv))
1910 			intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
1914 		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
1915 			intel_de_rmw(dev_priv,
1918 		else if (IS_ALDERLAKE_P(dev_priv))
1919 			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
1926 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1941 	val = intel_de_read(dev_priv, psr_iir_reg(dev_priv, cpu_transcoder));
1945 		drm_dbg_kms(&dev_priv->drm,
1958 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1961 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1981 		drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
1983 		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
2005 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2010 		if (transcoder_has_psr2(dev_priv, cpu_transcoder)) {
2011 			val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
2012 			drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
2015 		val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));
2016 		drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
2022 		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
2027 		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
2030 		drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
2032 		val = intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder),
2035 		drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
2042 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2051 		psr_status = psr_status_reg(dev_priv, cpu_transcoder);
2056 	if (intel_de_wait_for_clear(dev_priv, psr_status,
2058 		drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
2063 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2072 		drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");
2074 		drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
2084 	if (DISPLAY_VER(dev_priv) >= 11)
2085 		intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
2090 		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
2091 			intel_de_rmw(dev_priv,
2094 		else if (IS_ALDERLAKE_P(dev_priv))
2095 			intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
2104 		intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder),
2108 		intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
2137 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2142 	if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
2162 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2176 	drm_WARN_ON(&dev_priv->drm, psr->paused);
2213 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
2215 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ? 0 :
2219 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
2221 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
2226 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
2228 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
2233 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
2235 	return IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14 ?
2242 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2246 		intel_de_write(dev_priv,
2248 			       man_trk_ctl_enable_bit_get(dev_priv) |
2249 			       man_trk_ctl_partial_frame_bit_get(dev_priv) |
2250 			       man_trk_ctl_single_full_frame_bit_get(dev_priv) |
2251 			       man_trk_ctl_continuos_full_frame(dev_priv));
2266 	intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2272 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2279 	for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
2289 	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
2295 	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
2303 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2304 	u32 val = man_trk_ctl_enable_bit_get(dev_priv);
2307 	val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
2310 		val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
2311 		val |= man_trk_ctl_continuos_full_frame(dev_priv);
2318 	if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) {
2376 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2382 	    (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14))
2470 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2566 		drm_info_once(&dev_priv->drm,
2576 	if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
2577 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
2708 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2724 		drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
2730 		keep_disabled |= DISPLAY_VER(dev_priv) < 11 &&
2755 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2763 	return intel_de_wait_for_clear(dev_priv,
2770 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2779 	return intel_de_wait_for_clear(dev_priv,
2780 				       psr_status_reg(dev_priv, cpu_transcoder),
2793 	struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
2799 	for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
2815 			drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
2821 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2834 		reg = psr_status_reg(dev_priv, cpu_transcoder);
2840 	err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
2842 		drm_err(&dev_priv->drm,
2850 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
2858 	state = drm_atomic_state_alloc(&dev_priv->drm);
2868 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
2915 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2922 		drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
2943 		ret = intel_psr_fastset_force(dev_priv);
2995 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3003 			intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3007 		val = man_trk_ctl_enable_bit_get(dev_priv) |
3008 		      man_trk_ctl_partial_frame_bit_get(dev_priv) |
3009 		      man_trk_ctl_continuos_full_frame(dev_priv);
3010 		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), val);
3011 		intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3020  * @dev_priv: i915 device
3031 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
3039 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
3090 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3097 				u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
3098 					man_trk_ctl_partial_frame_bit_get(dev_priv) |
3099 					man_trk_ctl_single_full_frame_bit_get(dev_priv) |
3100 					man_trk_ctl_continuos_full_frame(dev_priv);
3108 				intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
3110 				intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3124 			queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
3130  * @dev_priv: i915 device
3141 void intel_psr_flush(struct drm_i915_private *dev_priv,
3146 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
3197 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3199 	if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
3211 	if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
3212 		drm_dbg_kms(&dev_priv->drm,
3217 	if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp))
3226 	if (DISPLAY_VER(dev_priv) < 12)
3263 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3274 		drm_err(&dev_priv->drm, "Error reading ALPM status\n");
3281 		drm_dbg_kms(&dev_priv->drm,
3291 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3298 		drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
3305 		drm_dbg_kms(&dev_priv->drm,
3322 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3338 		drm_err(&dev_priv->drm,
3351 		drm_dbg_kms(&dev_priv->drm,
3354 		drm_dbg_kms(&dev_priv->drm,
3357 		drm_dbg_kms(&dev_priv->drm,
3360 		drm_dbg_kms(&dev_priv->drm,
3364 		drm_err(&dev_priv->drm,
3444 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3463 		val = intel_de_read(dev_priv, EDP_PSR2_STATUS(cpu_transcoder));
3478 		val = intel_de_read(dev_priv, psr_status_reg(dev_priv, cpu_transcoder));
3489 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3507 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
3526 		val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
3529 		val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
3532 		val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));
3544 	val = intel_de_read(dev_priv, psr_perf_cnt_reg(dev_priv, cpu_transcoder));
3563 			val = intel_de_read(dev_priv, PSR2_SU_STATUS(cpu_transcoder, frame));
3584 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
3591 	struct drm_i915_private *dev_priv = m->private;
3595 	if (!HAS_PSR(dev_priv))
3599 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
3614 	struct drm_i915_private *dev_priv = data;
3619 	if (!HAS_PSR(dev_priv))
3622 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
3625 		drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val);
3627 		wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
3632 		intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
3641 	struct drm_i915_private *dev_priv = data;
3644 	if (!HAS_PSR(dev_priv))
3647 	for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {