Lines Matching defs:psr
192 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
193 (intel_dp)->psr.source_support)
209 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
212 return connector->panel.vbt.psr.enable;
225 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
241 EDP_PSR_ERROR(intel_dp->psr.transcoder);
249 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
257 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
265 EDP_PSR_MASK(intel_dp->psr.transcoder);
343 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
346 if (intel_dp->psr.panel_replay_enabled)
350 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
399 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
403 intel_dp->psr.last_entry_attempt = time_ns;
410 intel_dp->psr.last_exit = time_ns;
420 psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
428 intel_dp->psr.irq_aux_error = true;
441 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
505 intel_dp->psr.su_w_granularity = w;
506 intel_dp->psr.su_y_granularity = y;
514 intel_dp->psr.sink_panel_replay_support = false;
525 intel_dp->psr.sink_panel_replay_support = true;
548 intel_dp->psr.sink_support = true;
549 intel_dp->psr.sink_sync_latency =
569 intel_dp->psr.sink_psr2_support = y_req && alpm;
571 intel_dp->psr.sink_psr2_support ? "" : "not ");
585 if (intel_dp->psr.sink_psr2_support)
592 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
632 !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
640 return intel_dp->psr.panel_replay_enabled ?
668 if (intel_dp->psr.link_standby)
682 if (intel_dp->psr.entry_setup_frames > 0)
708 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
710 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
712 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
717 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
719 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
721 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
731 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&
732 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
754 idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
755 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
766 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
778 if (intel_dp->psr.link_standby)
787 val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
802 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
803 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
805 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
807 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
817 return intel_dp->psr.alpm_parameters.io_wake_lines < 9 &&
818 intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12;
831 intel_dp->psr.sink_sync_latency + 1,
835 if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)
836 frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;
845 intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
848 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
855 struct intel_psr *psr = &intel_dp->psr;
856 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
897 tmp = map[psr->alpm_parameters.io_wake_lines -
901 tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
904 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
905 val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
907 val |= EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
908 val |= EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
911 if (intel_dp->psr.req_psr2_sdp_prior_scanline)
915 psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);
917 if (intel_dp->psr.psr2_sel_fetch_enabled) {
964 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
990 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
992 mutex_lock(&intel_dp->psr.lock);
994 if (delayed_work_pending(&intel_dp->psr.dc3co_work))
999 mutex_unlock(&intel_dp->psr.lock);
1004 if (!intel_dp->psr.dc3co_exitline)
1007 cancel_delayed_work(&intel_dp->psr.dc3co_work);
1079 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
1107 if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
1110 if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
1115 return intel_dp->psr.su_y_granularity == 4;
1123 y_granularity = intel_dp->psr.su_y_granularity;
1124 else if (intel_dp->psr.su_y_granularity <= 2)
1126 else if ((intel_dp->psr.su_y_granularity % 4) == 0)
1127 y_granularity = intel_dp->psr.su_y_granularity;
1292 intel_dp->psr.alpm_parameters.fast_wake_lines = aux_less_wake_lines;
1293 intel_dp->psr.alpm_parameters.silence_period_sym_clocks = silence_period;
1294 intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle;
1321 intel_dp->psr.alpm_parameters.check_entry_lines = check_entry_lines;
1389 intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7);
1390 intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7);
1436 if (!intel_dp->psr.sink_psr2_support)
1588 intel_dp->psr.entry_setup_frames = entry_setup_frames;
1610 if (intel_dp->psr.sink_not_reliable) {
1661 mutex_lock(&intel_dp->psr.lock);
1662 if (!intel_dp->psr.enabled)
1665 if (intel_dp->psr.panel_replay_enabled) {
1675 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1678 if (!intel_dp->psr.psr2_enabled)
1692 mutex_unlock(&intel_dp->psr.lock);
1698 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1707 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1709 lockdep_assert_held(&intel_dp->psr.lock);
1712 if (intel_dp->psr.panel_replay_enabled)
1714 else if (intel_dp->psr.psr2_enabled)
1719 intel_dp->psr.active = true;
1724 switch (intel_dp->psr.pipe) {
1734 MISSING_CASE(intel_dp->psr.pipe);
1769 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1770 struct intel_psr *psr = &intel_dp->psr;
1773 if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled &&
1781 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
1791 psr->alpm_parameters.silence_period_sym_clocks));
1796 psr->alpm_parameters.lfps_half_cycle_num_of_syms) |
1798 psr->alpm_parameters.lfps_half_cycle_num_of_syms) |
1800 psr->alpm_parameters.lfps_half_cycle_num_of_syms));
1803 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines);
1806 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines);
1815 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1879 if (intel_dp->psr.dc3co_exitline)
1881 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
1885 intel_dp->psr.psr2_sel_fetch_enabled ?
1897 if (intel_dp->psr.psr2_enabled) {
1927 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1930 if (intel_dp->psr.panel_replay_enabled)
1944 intel_dp->psr.sink_not_reliable = true;
1961 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1963 intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1964 intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
1965 intel_dp->psr.busy_frontbuffer_bits = 0;
1966 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1967 intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1970 intel_dp->psr.dc3co_exit_delay = val;
1971 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1972 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1973 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1974 intel_dp->psr.req_psr2_sdp_prior_scanline =
1980 if (intel_dp->psr.panel_replay_enabled) {
1984 intel_dp->psr.psr2_enabled ? "2" : "1");
1997 intel_dp->psr.enabled = true;
1998 intel_dp->psr.paused = false;
2006 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2009 if (!intel_dp->psr.active) {
2021 if (intel_dp->psr.panel_replay_enabled) {
2022 intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
2024 } else if (intel_dp->psr.psr2_enabled) {
2037 intel_dp->psr.active = false;
2043 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2047 if (intel_dp->psr.psr2_enabled) {
2064 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2066 lockdep_assert_held(&intel_dp->psr.lock);
2068 if (!intel_dp->psr.enabled)
2071 if (intel_dp->psr.panel_replay_enabled)
2075 intel_dp->psr.psr2_enabled ? "2" : "1");
2088 if (intel_dp->psr.psr2_enabled) {
2103 if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) {
2116 if (!intel_dp->psr.panel_replay_enabled &&
2117 intel_dp->psr.psr2_enabled)
2120 intel_dp->psr.enabled = false;
2121 intel_dp->psr.panel_replay_enabled = false;
2122 intel_dp->psr.psr2_enabled = false;
2123 intel_dp->psr.psr2_sel_fetch_enabled = false;
2124 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2145 mutex_lock(&intel_dp->psr.lock);
2149 mutex_unlock(&intel_dp->psr.lock);
2150 cancel_work_sync(&intel_dp->psr.work);
2151 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
2158 * This function need to be called after enabling psr.
2163 struct intel_psr *psr = &intel_dp->psr;
2168 mutex_lock(&psr->lock);
2170 if (!psr->enabled) {
2171 mutex_unlock(&psr->lock);
2176 drm_WARN_ON(&dev_priv->drm, psr->paused);
2180 psr->paused = true;
2182 mutex_unlock(&psr->lock);
2184 cancel_work_sync(&psr->work);
2185 cancel_delayed_work_sync(&psr->dc3co_work);
2192 * This function need to be called after pausing psr.
2196 struct intel_psr *psr = &intel_dp->psr;
2201 mutex_lock(&psr->lock);
2203 if (!psr->paused)
2206 psr->paused = false;
2210 mutex_unlock(&psr->lock);
2243 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2245 if (intel_dp->psr.psr2_sel_fetch_enabled)
2266 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2283 lockdep_assert_held(&intel_dp->psr.lock);
2284 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
2676 struct intel_psr *psr = &intel_dp->psr;
2679 mutex_lock(&psr->lock);
2691 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
2695 if (psr->enabled && needs_to_disable)
2697 else if (psr->enabled && new_crtc_state->wm_level_disabled)
2701 mutex_unlock(&psr->lock);
2719 struct intel_psr *psr = &intel_dp->psr;
2722 mutex_lock(&psr->lock);
2724 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
2726 keep_disabled |= psr->sink_not_reliable;
2733 if (!psr->enabled && !keep_disabled)
2735 else if (psr->enabled && !crtc_state->wm_level_disabled)
2740 if (crtc_state->crc_enabled && psr->enabled)
2747 intel_dp->psr.busy_frontbuffer_bits = 0;
2749 mutex_unlock(&psr->lock);
2756 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2771 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2804 lockdep_assert_held(&intel_dp->psr.lock);
2806 if (!intel_dp->psr.enabled)
2809 if (intel_dp->psr.psr2_enabled)
2822 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2827 if (!intel_dp->psr.enabled)
2830 if (intel_dp->psr.psr2_enabled) {
2838 mutex_unlock(&intel_dp->psr.lock);
2846 mutex_lock(&intel_dp->psr.lock);
2847 return err == 0 && intel_dp->psr.enabled;
2926 ret = mutex_lock_interruptible(&intel_dp->psr.lock);
2930 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
2931 intel_dp->psr.debug = val;
2937 if (intel_dp->psr.enabled)
2940 mutex_unlock(&intel_dp->psr.lock);
2950 struct intel_psr *psr = &intel_dp->psr;
2953 psr->sink_not_reliable = true;
2961 container_of(work, typeof(*intel_dp), psr.work);
2963 mutex_lock(&intel_dp->psr.lock);
2965 if (!intel_dp->psr.enabled)
2968 if (READ_ONCE(intel_dp->psr.irq_aux_error))
2985 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2990 mutex_unlock(&intel_dp->psr.lock);
2996 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
2998 if (intel_dp->psr.psr2_sel_fetch_enabled) {
3001 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3003 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3011 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3012 intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
3043 mutex_lock(&intel_dp->psr.lock);
3044 if (!intel_dp->psr.enabled) {
3045 mutex_unlock(&intel_dp->psr.lock);
3050 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3051 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
3056 mutex_unlock(&intel_dp->psr.lock);
3071 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
3072 !intel_dp->psr.active)
3080 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
3084 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work,
3085 intel_dp->psr.dc3co_exit_delay);
3091 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3093 if (intel_dp->psr.psr2_sel_fetch_enabled) {
3094 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
3096 if (intel_dp->psr.busy_frontbuffer_bits == 0) {
3110 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3111 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
3123 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
3124 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work);
3150 mutex_lock(&intel_dp->psr.lock);
3151 if (!intel_dp->psr.enabled) {
3152 mutex_unlock(&intel_dp->psr.lock);
3157 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3158 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
3165 if (intel_dp->psr.paused)
3170 !intel_dp->psr.psr2_sel_fetch_enabled)) {
3181 mutex_unlock(&intel_dp->psr.lock);
3218 intel_dp->psr.source_panel_replay_support = true;
3220 intel_dp->psr.source_support = true;
3223 intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
3228 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
3230 INIT_WORK(&intel_dp->psr.work, intel_psr_work);
3231 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
3232 mutex_init(&intel_dp->psr.lock);
3242 offset = intel_dp->psr.panel_replay_enabled ?
3249 offset = intel_dp->psr.panel_replay_enabled ?
3265 struct intel_psr *psr = &intel_dp->psr;
3269 if (!psr->psr2_enabled)
3280 psr->sink_not_reliable = true;
3292 struct intel_psr *psr = &intel_dp->psr;
3304 psr->sink_not_reliable = true;
3323 struct intel_psr *psr = &intel_dp->psr;
3332 mutex_lock(&psr->lock);
3334 if (!psr->enabled)
3343 if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||
3346 psr->sink_not_reliable = true;
3349 if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&
3370 if (!psr->panel_replay_enabled) {
3376 mutex_unlock(&psr->lock);
3386 mutex_lock(&intel_dp->psr.lock);
3387 ret = intel_dp->psr.enabled;
3388 mutex_unlock(&intel_dp->psr.lock);
3413 mutex_lock(&intel_dp->psr.lock);
3436 mutex_unlock(&intel_dp->psr.lock);
3445 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3449 if (intel_dp->psr.psr2_enabled) {
3490 enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
3491 struct intel_psr *psr = &intel_dp->psr;
3498 str_yes_no(psr->sink_support));
3500 if (psr->sink_support)
3502 seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr->sink_panel_replay_support));
3504 if (!(psr->sink_support || psr->sink_panel_replay_support))
3508 mutex_lock(&psr->lock);
3510 if (psr->panel_replay_enabled)
3512 else if (psr->enabled)
3513 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
3518 if (!psr->enabled) {
3520 str_yes_no(psr->sink_not_reliable));
3525 if (psr->panel_replay_enabled) {
3528 } else if (psr->psr2_enabled) {
3539 psr->busy_frontbuffer_bits);
3548 if (psr->debug & I915_PSR_DEBUG_IRQ) {
3550 psr->last_entry_attempt);
3551 seq_printf(m, "Last exit at: %lld\n", psr->last_exit);
3554 if (psr->psr2_enabled) {
3579 str_enabled_disabled(psr->psr2_sel_fetch_enabled));
3583 mutex_unlock(&psr->lock);
3651 *val = READ_ONCE(intel_dp->psr.debug);
3675 if (intel_dp->psr.panel_replay_enabled)
3677 else if (intel_dp->psr.enabled)
3721 if (intel_dp->psr.panel_replay_enabled) {
3725 } else if (intel_dp->psr.enabled) {