i915/display/intel_psr.c

71  * must be correctly synchronized/cancelled when shutting down the pipe."
103  *  When unmasked (nearly) all pipe/plane register writes
1017 	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1022 		return pipe <= PIPE_B && port <= PORT_B;
1024 		return pipe == PIPE_A && port == PORT_A;
1483 			    "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
1503 			    "PSR2 not enabled, pipe bpp %d > max supported %d\n",
1724 	switch (intel_dp->psr.pipe) {
1734 		MISSING_CASE(intel_dp->psr.pipe);
1860 		 * No separate pipe reg write mask on hsw/bdw, so have to unmask all
1966 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
2132  * This function needs to be called before disabling pipe.
2260 	 * pipe.
2266 	intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2295 	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
2453  * Check for pipe properties that is not supported by selective fetch.
2455  * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
2492 	 * the pipe damaged area.
2494 	 * using whole pipe damaged area.
2567 			      "Selective fetch area calculation failed in pipe %c\n",
2568 			      pipe_name(crtc->pipe));
2596 	 * Now that we have the pipe damaged area check if it intersect with
2785  * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
2891 		/* Mark mode as changed to trigger a pipe->update() */
3003 			intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3011 		intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3050 			INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3080 	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
3110 				intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
3157 			INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
3422  * Release the PSR lock that was held during pipe update.