i915/display/intel_pps.c

27 static const char *pps_name(struct drm_i915_private *i915,
30 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
346 static int intel_num_pps(struct drm_i915_private *i915)
348 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
351 	if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
354 	if (INTEL_PCH_TYPE(i915) >= PCH_DG1)
357 	if (INTEL_PCH_TYPE(i915) >= PCH_ICP)
365 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
368 	    INTEL_PCH_TYPE(i915) >= PCH_ICP &&
369 	    INTEL_PCH_TYPE(i915) <= PCH_ADP)
370 		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;
376 bxt_initial_pps_idx(struct drm_i915_private *i915, pps_check check)
378 	int pps_idx, pps_num = intel_num_pps(i915);
381 		if (check(i915, pps_idx))
393 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
395 	lockdep_assert_held(&i915->display.pps.mutex);
397 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
403 	if (intel_num_pps(i915) > 1)
408 	if (drm_WARN_ON(&i915->drm, intel_dp->pps.pps_idx >= intel_num_pps(i915)))
413 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_pp_on);
416 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_has_vdd_on);
419 		intel_dp->pps.pps_idx = bxt_initial_pps_idx(i915, pps_any);
421 		drm_dbg_kms(&i915->drm,
424 			    pps_name(i915, &intel_dp->pps));
426 		drm_dbg_kms(&i915->drm,
429 			    pps_name(i915, &intel_dp->pps));
621 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
624 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power on\n",
626 		    pps_name(i915, &intel_dp->pps));
632 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
635 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power off time\n",
637 		    pps_name(i915, &intel_dp->pps));
643 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
648 	drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] %s wait for panel power cycle\n",
650 		    pps_name(i915, &intel_dp->pps));
779 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
789 	I915_STATE_WARN(i915, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n",
792 			pps_name(i915, &intel_dp->pps));
869 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
885 	queue_delayed_work(i915->unordered_wq,
1089 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
1100 	drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
1258 	 * and removed i915, which has already ensured sufficient power off
1305 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1307 	drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
1315 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1323 		drm_err(&i915->drm, "PPS state mismatch\n");
1560 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1571 		if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1606 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1610 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1613 	if (intel_num_pps(i915) < 2)
1616 	drm_WARN(&i915->drm, connector->panel.vbt.backlight.controller >= 0 &&
1663 void intel_pps_setup(struct drm_i915_private *i915)
1665 	if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
1666 		i915->display.pps.mmio_base = PCH_PPS_BASE;
1667 	else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
1668 		i915->display.pps.mmio_base = VLV_PPS_BASE;
1670 		i915->display.pps.mmio_base = PPS_BASE;