i915/display/intel_pch_refclk.c

13 static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
15 	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
17 	if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
19 		drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
21 	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
23 	if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
25 		drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n");
29 static void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
33 	lpt_fdi_reset_mphy(dev_priv);
35 	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
38 	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
40 	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
42 	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
44 	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
46 	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
48 	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
50 	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
52 	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
54 	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
56 	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
59 	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
61 	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
64 	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
66 	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
69 	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
71 	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
74 	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
76 	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
79 	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
81 	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
84 	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
86 	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
88 	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
90 	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
92 	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
94 	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
97 	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
99 	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
102 	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
105 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
109 	intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE);
111 	mutex_lock(&dev_priv->sb_lock);
113 	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
115 	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
117 	mutex_unlock(&dev_priv->sb_lock);
178 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
183 	lpt_disable_iclkip(dev_priv);
186 	drm_WARN_ON(&dev_priv->drm, lpt_iclkip_freq(&p) != clock);
189 	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) &
191 	drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(p.phasedir) &
194 	drm_dbg_kms(&dev_priv->drm,
198 	mutex_lock(&dev_priv->sb_lock);
201 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
208 	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
211 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
214 	intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
217 	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
219 	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
221 	mutex_unlock(&dev_priv->sb_lock);
226 	intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE);
229 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
234 	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
239 	mutex_lock(&dev_priv->sb_lock);
241 	temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
243 		mutex_unlock(&dev_priv->sb_lock);
247 	temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
253 	temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
257 	mutex_unlock(&dev_priv->sb_lock);
270 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
275 	if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,
278 	if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&
282 	mutex_lock(&dev_priv->sb_lock);
284 	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
287 	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
292 		tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
294 		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
297 			lpt_fdi_program_mphy(dev_priv);
300 	reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
301 	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
303 	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
305 	mutex_unlock(&dev_priv->sb_lock);
309 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
313 	mutex_lock(&dev_priv->sb_lock);
315 	reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
316 	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
318 	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
320 	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
324 			intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
328 		intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
331 	mutex_unlock(&dev_priv->sb_lock);
366 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
371 	if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))
374 	if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase)))
377 	mutex_lock(&dev_priv->sb_lock);
383 	intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
385 	tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
388 	intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
390 	mutex_unlock(&dev_priv->sb_lock);
395 static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
397 	u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
398 	u32 ctl = intel_de_read(dev_priv, SPLL_CTL);
407 	if (IS_BROADWELL(dev_priv) &&
414 static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
417 	u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
418 	u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id));
426 	if ((IS_BROADWELL(dev_priv) || IS_HASWELL_ULT(dev_priv)) &&
434 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
439 	for_each_intel_encoder(&dev_priv->drm, encoder) {
464 	dev_priv->display.dpll.pch_ssc_use = 0;
466 	if (spll_uses_pch_ssc(dev_priv)) {
467 		drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n");
468 		dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);
471 	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) {
472 		drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n");
473 		dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);
476 	if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) {
477 		drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n");
478 		dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);
481 	if (dev_priv->display.dpll.pch_ssc_use)
485 		lpt_bend_clkout_dp(dev_priv, 0);
486 		lpt_enable_clkout_dp(dev_priv, true, true);
488 		lpt_disable_clkout_dp(dev_priv);
492 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
506 	for_each_intel_encoder(&dev_priv->drm, encoder) {
522 	if (HAS_PCH_IBX(dev_priv)) {
523 		has_ck505 = dev_priv->display.vbt.display_clock_mode;
531 	for_each_shared_dpll(dev_priv, pll, i) {
534 		temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
546 	drm_dbg_kms(&dev_priv->drm,
555 	val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
575 		if (intel_panel_use_ssc(dev_priv) && can_ssc)
579 			if (intel_panel_use_ssc(dev_priv) && can_ssc)
607 		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
608 			drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n");
615 		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
616 		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
623 			if (intel_panel_use_ssc(dev_priv) && can_ssc) {
624 				drm_dbg_kms(&dev_priv->drm,
634 		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
635 		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
638 		drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
645 		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
646 		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
650 			drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
659 			intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
660 			intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
665 	drm_WARN_ON(&dev_priv->drm, val != final);
671 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
673 	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
674 		ilk_init_pch_refclk(dev_priv);
675 	else if (HAS_PCH_LPT(dev_priv))
676 		lpt_init_pch_refclk(dev_priv);