i915/display/intel_overlay.c

208 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
211 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
216 		intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0);
218 		intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv),
256 	struct drm_i915_private *dev_priv = overlay->i915;
260 	drm_WARN_ON(&dev_priv->drm, overlay->active);
274 	if (IS_I830(dev_priv))
275 		i830_overlay_clock_gating(dev_priv, false);
321 	struct drm_i915_private *dev_priv = overlay->i915;
326 	drm_WARN_ON(&dev_priv->drm, !overlay->active);
332 	tmp = intel_de_read(dev_priv, DOVSTA);
334 		drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
379 	struct drm_i915_private *dev_priv = overlay->i915;
387 	if (IS_I830(dev_priv))
388 		i830_overlay_clock_gating(dev_priv, true);
455 	struct drm_i915_private *dev_priv = overlay->i915;
466 	if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
490 void intel_overlay_reset(struct drm_i915_private *dev_priv)
492 	struct intel_overlay *overlay = dev_priv->display.overlay;
553 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
557 	if (DISPLAY_VER(dev_priv) == 2)
793 	struct drm_i915_private *dev_priv = overlay->i915;
800 	drm_WARN_ON(&dev_priv->drm,
801 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
807 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
827 		if (DISPLAY_VER(dev_priv) == 4)
848 	swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
861 		tmp_U = calc_swidthsw(dev_priv, params->offset_U,
863 		tmp_V = calc_swidthsw(dev_priv, params->offset_V,
895 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
902 	struct drm_i915_private *dev_priv = overlay->i915;
905 	drm_WARN_ON(&dev_priv->drm,
906 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
939 	struct drm_i915_private *dev_priv = overlay->i915;
945 	if (DISPLAY_VER(dev_priv) >= 4) {
946 		u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
953 		if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE)
954 			tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
956 			tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
1001 static int check_overlay_src(struct drm_i915_private *dev_priv,
1012 	if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
1064 	if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1071 	if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
1116 	struct drm_i915_private *dev_priv = to_i915(dev);
1123 	overlay = dev_priv->display.overlay;
1125 		drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1149 		drm_dbg_kms(&dev_priv->drm,
1198 	ret = check_overlay_src(dev_priv, params, new_bo);
1279 	struct drm_i915_private *dev_priv = to_i915(dev);
1283 	overlay = dev_priv->display.overlay;
1285 		drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1298 		if (DISPLAY_VER(dev_priv) != 2) {
1299 			attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
1300 			attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
1301 			attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
1302 			attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
1303 			attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
1304 			attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
1322 			if (DISPLAY_VER(dev_priv) == 2)
1334 			intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
1335 			intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
1336 			intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
1337 			intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
1338 			intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
1339 			intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
1391 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1397 	if (!HAS_OVERLAY(dev_priv))
1400 	engine = to_gt(dev_priv)->engine[RCS0];
1408 	overlay->i915 = dev_priv;
1419 	ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1427 	dev_priv->display.overlay = overlay;
1428 	drm_info(&dev_priv->drm, "Initialized overlay support.\n");
1435 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1439 	overlay = fetch_and_zero(&dev_priv->display.overlay);
1448 	drm_WARN_ON(&dev_priv->drm, overlay->active);
1466 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1468 	struct intel_overlay *overlay = dev_priv->display.overlay;
1478 	error->dovsta = intel_de_read(dev_priv, DOVSTA);
1479 	error->isr = intel_de_read(dev_priv, GEN2_ISR);