i915/display/intel_fifo_underrun.c

60 	struct drm_i915_private *dev_priv = to_i915(dev);
64 	lockdep_assert_held(&dev_priv->irq_lock);
66 	for_each_pipe(dev_priv, pipe) {
67 		crtc = intel_crtc_for_pipe(dev_priv, pipe);
78 	struct drm_i915_private *dev_priv = to_i915(dev);
82 	lockdep_assert_held(&dev_priv->irq_lock);
84 	for_each_pipe(dev_priv, pipe) {
85 		crtc = intel_crtc_for_pipe(dev_priv, pipe);
96 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
100 	lockdep_assert_held(&dev_priv->irq_lock);
102 	if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
105 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
106 	intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
107 	intel_de_posting_read(dev_priv, reg);
109 	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);
110 	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));
117 	struct drm_i915_private *dev_priv = to_i915(dev);
120 	lockdep_assert_held(&dev_priv->irq_lock);
123 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
125 		intel_de_write(dev_priv, reg,
127 		intel_de_posting_read(dev_priv, reg);
129 		if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS)
130 			drm_err(&dev_priv->drm, "pipe %c underrun\n",
138 	struct drm_i915_private *dev_priv = to_i915(dev);
143 		ilk_enable_display_irq(dev_priv, bit);
145 		ilk_disable_display_irq(dev_priv, bit);
150 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
152 	u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT);
154 	lockdep_assert_held(&dev_priv->irq_lock);
159 	intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
160 	intel_de_posting_read(dev_priv, GEN7_ERR_INT);
162 	trace_intel_cpu_fifo_underrun(dev_priv, pipe);
163 	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));
170 	struct drm_i915_private *dev_priv = to_i915(dev);
172 		intel_de_write(dev_priv, GEN7_ERR_INT,
178 		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
180 		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
183 		    intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
184 			drm_err(&dev_priv->drm,
192 icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv)
196 	if (DISPLAY_VER(dev_priv) >= 13)
207 	struct drm_i915_private *dev_priv = to_i915(dev);
208 	u32 mask = gen8_de_pipe_underrun_mask(dev_priv);
211 		if (DISPLAY_VER(dev_priv) >= 11)
212 			intel_de_write(dev_priv, ICL_PIPESTATUS(pipe),
213 				       icl_pipe_status_underrun_mask(dev_priv));
215 		bdw_enable_pipe_irq(dev_priv, pipe, mask);
217 		bdw_disable_pipe_irq(dev_priv, pipe, mask);
225 	struct drm_i915_private *dev_priv = to_i915(dev);
230 		ibx_enable_display_interrupt(dev_priv, bit);
232 		ibx_disable_display_interrupt(dev_priv, bit);
237 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
239 	u32 serr_int = intel_de_read(dev_priv, SERR_INT);
241 	lockdep_assert_held(&dev_priv->irq_lock);
246 	intel_de_write(dev_priv, SERR_INT,
248 	intel_de_posting_read(dev_priv, SERR_INT);
250 	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
251 	drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n",
259 	struct drm_i915_private *dev_priv = to_i915(dev);
262 		intel_de_write(dev_priv, SERR_INT,
268 		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
270 		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
272 		if (old && intel_de_read(dev_priv, SERR_INT) &
274 			drm_err(&dev_priv->drm,
284 	struct drm_i915_private *dev_priv = to_i915(dev);
285 	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
288 	lockdep_assert_held(&dev_priv->irq_lock);
293 	if (HAS_GMCH(dev_priv))
295 	else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
297 	else if (DISPLAY_VER(dev_priv) == 7)
299 	else if (DISPLAY_VER(dev_priv) >= 8)
307  * @dev_priv: i915 device instance
321 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
327 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
328 	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,
330 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
337  * @dev_priv: i915 device instance
349 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
354 		intel_crtc_for_pipe(dev_priv, pch_transcoder);
367 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
372 	if (HAS_PCH_IBX(dev_priv))
373 		ibx_set_fifo_underrun_reporting(&dev_priv->drm,
377 		cpt_set_fifo_underrun_reporting(&dev_priv->drm,
381 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
387  * @dev_priv: i915 device instance
394 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
397 	struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
405 	if (HAS_GMCH(dev_priv) &&
420 	if (DISPLAY_VER(dev_priv) >= 11) {
421 		underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &
422 			icl_pipe_status_underrun_mask(dev_priv);
423 		intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);
426 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
427 		trace_intel_cpu_fifo_underrun(dev_priv, pipe);
429 		if (DISPLAY_VER(dev_priv) >= 11)
430 			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n",
437 			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
440 	intel_fbc_handle_fifo_underrun_irq(dev_priv);
445  * @dev_priv: i915 device instance
452 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
455 	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,
457 		trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);
458 		drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n",
465  * @dev_priv: i915 device instance
472 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)
476 	spin_lock_irq(&dev_priv->irq_lock);
478 	for_each_intel_crtc(&dev_priv->drm, crtc) {
482 		if (HAS_GMCH(dev_priv))
484 		else if (DISPLAY_VER(dev_priv) == 7)
488 	spin_unlock_irq(&dev_priv->irq_lock);
493  * @dev_priv: i915 device instance
499 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)
503 	spin_lock_irq(&dev_priv->irq_lock);
505 	for_each_intel_crtc(&dev_priv->drm, crtc) {
509 		if (HAS_PCH_CPT(dev_priv))
513 	spin_unlock_irq(&dev_priv->irq_lock);