i915/display/intel_fdi.c

467 	i915_reg_t reg;
471 	reg = FDI_TX_CTL(pipe);
472 	temp = intel_de_read(dev_priv, reg);
480 	intel_de_write(dev_priv, reg, temp);
482 	reg = FDI_RX_CTL(pipe);
483 	temp = intel_de_read(dev_priv, reg);
491 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
494 	intel_de_posting_read(dev_priv, reg);
499 		intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
509 	i915_reg_t reg;
524 	reg = FDI_RX_IMR(pipe);
525 	temp = intel_de_read(dev_priv, reg);
528 	intel_de_write(dev_priv, reg, temp);
529 	intel_de_read(dev_priv, reg);
533 	reg = FDI_TX_CTL(pipe);
534 	temp = intel_de_read(dev_priv, reg);
539 	intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
541 	reg = FDI_RX_CTL(pipe);
542 	temp = intel_de_read(dev_priv, reg);
545 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
547 	intel_de_posting_read(dev_priv, reg);
556 	reg = FDI_RX_IIR(pipe);
558 		temp = intel_de_read(dev_priv, reg);
563 			intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
578 	reg = FDI_RX_IIR(pipe);
580 		temp = intel_de_read(dev_priv, reg);
584 			intel_de_write(dev_priv, reg,
611 	i915_reg_t reg;
623 	reg = FDI_RX_IMR(pipe);
624 	temp = intel_de_read(dev_priv, reg);
627 	intel_de_write(dev_priv, reg, temp);
629 	intel_de_posting_read(dev_priv, reg);
633 	reg = FDI_TX_CTL(pipe);
634 	temp = intel_de_read(dev_priv, reg);
642 	intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
647 	reg = FDI_RX_CTL(pipe);
648 	temp = intel_de_read(dev_priv, reg);
656 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
658 	intel_de_posting_read(dev_priv, reg);
668 			reg = FDI_RX_IIR(pipe);
669 			temp = intel_de_read(dev_priv, reg);
672 				intel_de_write(dev_priv, reg,
687 	reg = FDI_TX_CTL(pipe);
688 	temp = intel_de_read(dev_priv, reg);
696 	intel_de_write(dev_priv, reg, temp);
698 	reg = FDI_RX_CTL(pipe);
699 	temp = intel_de_read(dev_priv, reg);
707 	intel_de_write(dev_priv, reg, temp);
709 	intel_de_posting_read(dev_priv, reg);
719 			reg = FDI_RX_IIR(pipe);
720 			temp = intel_de_read(dev_priv, reg);
723 				intel_de_write(dev_priv, reg,
747 	i915_reg_t reg;
761 	reg = FDI_RX_IMR(pipe);
762 	temp = intel_de_read(dev_priv, reg);
765 	intel_de_write(dev_priv, reg, temp);
767 	intel_de_posting_read(dev_priv, reg);
776 		reg = FDI_TX_CTL(pipe);
777 		temp = intel_de_read(dev_priv, reg);
780 		intel_de_write(dev_priv, reg, temp);
782 		reg = FDI_RX_CTL(pipe);
783 		temp = intel_de_read(dev_priv, reg);
787 		intel_de_write(dev_priv, reg, temp);
790 		reg = FDI_TX_CTL(pipe);
791 		temp = intel_de_read(dev_priv, reg);
798 		intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
803 		reg = FDI_RX_CTL(pipe);
804 		temp = intel_de_read(dev_priv, reg);
807 		intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
809 		intel_de_posting_read(dev_priv, reg);
813 			reg = FDI_RX_IIR(pipe);
814 			temp = intel_de_read(dev_priv, reg);
818 			    (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
819 				intel_de_write(dev_priv, reg,
845 			reg = FDI_RX_IIR(pipe);
846 			temp = intel_de_read(dev_priv, reg);
850 			    (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
851 				intel_de_write(dev_priv, reg,
1029 	i915_reg_t reg;
1033 	reg = FDI_RX_CTL(pipe);
1034 	temp = intel_de_read(dev_priv, reg);
1038 	intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
1040 	intel_de_posting_read(dev_priv, reg);
1044 	intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
1045 	intel_de_posting_read(dev_priv, reg);
1049 	reg = FDI_TX_CTL(pipe);
1050 	temp = intel_de_read(dev_priv, reg);
1052 		intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
1054 		intel_de_posting_read(dev_priv, reg);
1083 	i915_reg_t reg;
1090 	reg = FDI_RX_CTL(pipe);
1091 	temp = intel_de_read(dev_priv, reg);
1094 	intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
1096 	intel_de_posting_read(dev_priv, reg);
1108 	reg = FDI_RX_CTL(pipe);
1109 	temp = intel_de_read(dev_priv, reg);
1120 	intel_de_write(dev_priv, reg, temp);
1122 	intel_de_posting_read(dev_priv, reg);