i915/display/intel_fdi.c

24 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
29 	if (HAS_DDI(dev_priv)) {
37 		cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
39 		cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
41 	I915_STATE_WARN(dev_priv, cur_state != state,
56 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
61 	cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE;
62 	I915_STATE_WARN(dev_priv, cur_state != state,
119 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
121 	dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
184 	struct drm_i915_private *dev_priv = to_i915(dev);
191 	drm_dbg_kms(&dev_priv->drm,
195 		drm_dbg_kms(&dev_priv->drm,
201 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
203 			drm_dbg_kms(&dev_priv->drm,
212 	if (INTEL_NUM_PIPES(dev_priv) == 2)
223 		other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_C);
230 			drm_dbg_kms(&dev_priv->drm,
238 			drm_dbg_kms(&dev_priv->drm,
244 		other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B);
251 			drm_dbg_kms(&dev_priv->drm,
413 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
417 	temp = intel_de_read(dev_priv, SOUTH_CHICKEN1);
421 	drm_WARN_ON(&dev_priv->drm,
422 		    intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &
424 	drm_WARN_ON(&dev_priv->drm,
425 		    intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &
432 	drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",
434 	intel_de_write(dev_priv, SOUTH_CHICKEN1, temp);
435 	intel_de_posting_read(dev_priv, SOUTH_CHICKEN1);
441 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
448 			cpt_set_fdi_bc_bifurcation(dev_priv, false);
450 			cpt_set_fdi_bc_bifurcation(dev_priv, true);
454 		cpt_set_fdi_bc_bifurcation(dev_priv, true);
465 	struct drm_i915_private *dev_priv = to_i915(dev);
472 	temp = intel_de_read(dev_priv, reg);
473 	if (IS_IVYBRIDGE(dev_priv)) {
480 	intel_de_write(dev_priv, reg, temp);
483 	temp = intel_de_read(dev_priv, reg);
484 	if (HAS_PCH_CPT(dev_priv)) {
491 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
494 	intel_de_posting_read(dev_priv, reg);
498 	if (IS_IVYBRIDGE(dev_priv))
499 		intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE);
507 	struct drm_i915_private *dev_priv = to_i915(dev);
516 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
517 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
520 	assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder);
525 	temp = intel_de_read(dev_priv, reg);
528 	intel_de_write(dev_priv, reg, temp);
529 	intel_de_read(dev_priv, reg);
534 	temp = intel_de_read(dev_priv, reg);
539 	intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
542 	temp = intel_de_read(dev_priv, reg);
545 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
547 	intel_de_posting_read(dev_priv, reg);
551 	intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
553 	intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
558 		temp = intel_de_read(dev_priv, reg);
559 		drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
562 			drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n");
563 			intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK);
568 		drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
571 	intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
573 	intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
575 	intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
580 		temp = intel_de_read(dev_priv, reg);
581 		drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
584 			intel_de_write(dev_priv, reg,
586 			drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n");
591 		drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
593 	drm_dbg_kms(&dev_priv->drm, "FDI train done\n");
609 	struct drm_i915_private *dev_priv = to_i915(dev);
618 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
619 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
624 	temp = intel_de_read(dev_priv, reg);
627 	intel_de_write(dev_priv, reg, temp);
629 	intel_de_posting_read(dev_priv, reg);
634 	temp = intel_de_read(dev_priv, reg);
642 	intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
644 	intel_de_write(dev_priv, FDI_RX_MISC(pipe),
648 	temp = intel_de_read(dev_priv, reg);
649 	if (HAS_PCH_CPT(dev_priv)) {
656 	intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
658 	intel_de_posting_read(dev_priv, reg);
662 		intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
664 		intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
669 			temp = intel_de_read(dev_priv, reg);
670 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
672 				intel_de_write(dev_priv, reg,
674 				drm_dbg_kms(&dev_priv->drm,
684 		drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
688 	temp = intel_de_read(dev_priv, reg);
691 	if (IS_SANDYBRIDGE(dev_priv)) {
696 	intel_de_write(dev_priv, reg, temp);
699 	temp = intel_de_read(dev_priv, reg);
700 	if (HAS_PCH_CPT(dev_priv)) {
707 	intel_de_write(dev_priv, reg, temp);
709 	intel_de_posting_read(dev_priv, reg);
713 		intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
715 		intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
720 			temp = intel_de_read(dev_priv, reg);
721 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
723 				intel_de_write(dev_priv, reg,
725 				drm_dbg_kms(&dev_priv->drm,
735 		drm_err(&dev_priv->drm, "FDI train 2 fail!\n");
737 	drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
745 	struct drm_i915_private *dev_priv = to_i915(dev);
756 	intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe),
757 		       intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
762 	temp = intel_de_read(dev_priv, reg);
765 	intel_de_write(dev_priv, reg, temp);
767 	intel_de_posting_read(dev_priv, reg);
770 	drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",
771 		    intel_de_read(dev_priv, FDI_RX_IIR(pipe)));
777 		temp = intel_de_read(dev_priv, reg);
780 		intel_de_write(dev_priv, reg, temp);
783 		temp = intel_de_read(dev_priv, reg);
787 		intel_de_write(dev_priv, reg, temp);
791 		temp = intel_de_read(dev_priv, reg);
798 		intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE);
800 		intel_de_write(dev_priv, FDI_RX_MISC(pipe),
804 		temp = intel_de_read(dev_priv, reg);
807 		intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE);
809 		intel_de_posting_read(dev_priv, reg);
814 			temp = intel_de_read(dev_priv, reg);
815 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
818 			    (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) {
819 				intel_de_write(dev_priv, reg,
821 				drm_dbg_kms(&dev_priv->drm,
829 			drm_dbg_kms(&dev_priv->drm,
835 		intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
838 		intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
841 		intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
846 			temp = intel_de_read(dev_priv, reg);
847 			drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp);
850 			    (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) {
851 				intel_de_write(dev_priv, reg,
853 				drm_dbg_kms(&dev_priv->drm,
861 			drm_dbg_kms(&dev_priv->drm,
866 	drm_dbg_kms(&dev_priv->drm, "FDI train done.\n");
881 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
896 	intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
903 	rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
906 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
907 	intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
912 	intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
915 	drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL);
922 		intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
932 		intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
936 		intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
941 		intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
945 		intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
946 		intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
952 		intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
954 		intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
959 		temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
961 			drm_dbg_kms(&dev_priv->drm,
971 			drm_err(&dev_priv->drm, "FDI link training failed!\n");
976 		intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
977 		intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
979 		intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
980 		intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
983 		intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0);
984 		intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
986 		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
989 		intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
992 		intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
996 	intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1005 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1013 	intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
1014 	intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
1015 	intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1017 	intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
1020 	intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
1021 	intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
1027 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1034 	temp = intel_de_read(dev_priv, reg);
1037 	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
1038 	intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
1040 	intel_de_posting_read(dev_priv, reg);
1044 	intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
1045 	intel_de_posting_read(dev_priv, reg);
1050 	temp = intel_de_read(dev_priv, reg);
1052 		intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE);
1054 		intel_de_posting_read(dev_priv, reg);
1062 	struct drm_i915_private *dev_priv = to_i915(dev);
1066 	intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
1069 	intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
1070 	intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
1074 	intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
1075 	intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
1081 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1087 	intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
1088 	intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
1091 	temp = intel_de_read(dev_priv, reg);
1093 	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
1094 	intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
1096 	intel_de_posting_read(dev_priv, reg);
1100 	if (HAS_PCH_IBX(dev_priv))
1101 		intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe),
1105 	intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
1109 	temp = intel_de_read(dev_priv, reg);
1110 	if (HAS_PCH_CPT(dev_priv)) {
1119 	temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
1120 	intel_de_write(dev_priv, reg, temp);
1122 	intel_de_posting_read(dev_priv, reg);
1139 intel_fdi_init_hook(struct drm_i915_private *dev_priv)
1141 	if (IS_IRONLAKE(dev_priv)) {
1142 		dev_priv->display.funcs.fdi = &ilk_funcs;
1143 	} else if (IS_SANDYBRIDGE(dev_priv)) {
1144 		dev_priv->display.funcs.fdi = &gen6_funcs;
1145 	} else if (IS_IVYBRIDGE(dev_priv)) {
1147 		dev_priv->display.funcs.fdi = &ivb_funcs;