i915/display/intel_dsi_vbt.c

37 #include <drm/drm_crtc.h>
38 #include <drm/drm_edid.h>
111 	drm_dbg_kms(&dev_priv->drm, "\n");
123 	if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
128 		drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
153 		drm_dbg(&dev_priv->drm,
166 		drm_dbg(&dev_priv->drm,
188 	drm_dbg_kms(&i915->drm, "%d usecs\n", delay);
207 		gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, con_id, idx,
210 			drm_err(&dev_priv->drm,
250 			drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n");
254 			drm_dbg_kms(&dev_priv->drm,
287 			drm_dbg_kms(&dev_priv->drm,
293 			drm_dbg_kms(&dev_priv->drm,
328 	if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
418 	drm_dbg_kms(&i915->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n",
496 	drm_dbg_kms(&i915->drm, "bus %d client-addr 0x%02x reg 0x%02x data %*ph\n",
506 		drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n");
524 		drm_err(&i915->drm,
539 	drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");
562 		drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret);
564 	drm_err(&i915->drm,
619 	if (drm_WARN_ON(&dev_priv->drm,
627 	drm_WARN_ON(&dev_priv->drm, *data != seq_id);
629 	drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",
659 				drm_err(&dev_priv->drm,
665 			drm_dbg_kms(&dev_priv->drm,
671 			drm_err(&dev_priv->drm,
699 	drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk);
700 	drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",
702 	drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count);
703 	drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
704 	drm_dbg_kms(&i915->drm, "Video mode format %s\n",
711 	drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",
713 	drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val);
714 	drm_dbg_kms(&i915->drm, "Eot %s\n",
716 	drm_dbg_kms(&i915->drm, "Clockstop %s\n",
718 	drm_dbg_kms(&i915->drm, "Mode %s\n",
721 		drm_dbg_kms(&i915->drm,
724 		drm_dbg_kms(&i915->drm,
727 		drm_dbg_kms(&i915->drm, "Dual link: NONE\n");
728 	drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format);
729 	drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div);
730 	drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",
732 	drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",
734 	drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count);
735 	drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",
737 	drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
738 	drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
739 	drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",
741 	drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",
743 	drm_dbg_kms(&i915->drm, "BTA %s\n",
758 	drm_dbg_kms(&dev_priv->drm, "\n");
805 			drm_err(&dev_priv->drm, "Burst mode target is not set\n");
822 			drm_err(&dev_priv->drm, "Burst mode freq is less than computed\n");
912 			drm_err(&dev_priv->drm,
917 			drm_err(&dev_priv->drm,
927 			drm_err(&dev_priv->drm,
937 			drm_err(&dev_priv->drm,