i915/display/intel_dpll_mgr.c

179 	if (drm_WARN(&i915->drm, !pll,
260 	if (drm_WARN_ON(&i915->drm, pll == NULL))
266 	if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
267 	    drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
272 	drm_dbg_kms(&i915->drm,
278 		drm_WARN_ON(&i915->drm, !pll->on);
282 	drm_WARN_ON(&i915->drm, pll->on);
284 	drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
313 	if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
318 	drm_dbg_kms(&i915->drm,
324 	drm_WARN_ON(&i915->drm, !pll->on);
330 	drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
346 		drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
368 	drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
387 			drm_dbg_kms(&i915->drm,
399 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
423 	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
427 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
462 	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
466 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
619 		drm_dbg_kms(&i915->drm,
1081 		drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
1135 		drm_WARN(&i915->drm, 1, "bad port clock sel\n");
1188 		drm_WARN(&i915->drm, 1, "bad spll freq\n");
1393 		drm_err(&i915->drm, "DPLL %d not locked\n", id);
1479 	if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
1764 		drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
1798 	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
1908 		drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
2055 			drm_err(&i915->drm,
2118 		drm_err(&i915->drm, "PLL %d not locked\n", port);
2151 			drm_err(&i915->drm,
2222 		drm_dbg(&i915->drm,
2263 	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
2284 	drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
2315 		drm_err(&i915->drm, "Invalid VCO\n");
2433 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
2759 	drm_WARN_ON(&i915->drm, 1);
2878 	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
3783 	drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
3911 		drm_err(&i915->drm, "PLL %d Power not enabled\n",
3923 		drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
3946 	if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
3947 		drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
4036 		drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
4047 		drm_err(&i915->drm, "PLL %d Power not disabled\n",
4341 		if (drm_WARN_ON(&i915->drm,
4346 		if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
4378 	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4411 	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4463 	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
4481 	if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
4513 	for_each_intel_crtc(&i915->drm, crtc) {
4522 	drm_dbg_kms(&i915->drm,
4553 	drm_dbg_kms(&i915->drm,
4571  * @i915: i915 drm device
4593  * @i915: i915 drm device