Lines Matching refs:clk_div
2251 struct dpll *clk_div)
2260 if (!bxt_find_best_dpll(crtc_state, clk_div))
2263 drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
2269 struct dpll *clk_div)
2274 *clk_div = bxt_dp_clk_val[0];
2277 *clk_div = bxt_dp_clk_val[i];
2282 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
2284 drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
2285 clk_div->dot != crtc_state->port_clock);
2289 const struct dpll *clk_div)
2294 int vco = clk_div->vco;
2330 hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
2331 hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
2332 hw_state->pll1 = PORT_PLL_N(clk_div->n);
2333 hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
2335 if (clk_div->m2 & 0x3fffff)
2378 struct dpll clk_div = {};
2380 bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
2382 return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2389 struct dpll clk_div = {};
2392 bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
2394 ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);