i915/display/intel_dpll_mgr.c

1135 		drm_WARN(&i915->drm, 1, "bad port clock sel\n");
2039 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2044 	bxt_port_to_phy_channel(i915, port, &phy, &ch);
2047 	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
2050 		intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
2053 		if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
2056 				"Power state not set for PLL:%d\n", port);
2113 	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
2114 	intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
2116 	if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
2118 		drm_err(&i915->drm, "PLL %d not locked\n", port);
2140 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2142 	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
2143 	intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
2146 		intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
2149 		if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
2152 				"Power state not reset for PLL:%d\n", port);
2161 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2168 	bxt_port_to_phy_channel(i915, port, &phy, &ch);
2177 	val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
2430 	id = (enum intel_dpll_id) encoder->port;
3269  * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3347 	enum port port = encoder->port;
3357 		if (port == PORT_D || port == PORT_E) {
3372 		   port != PORT_A) {
3489 	MISSING_CASE(encoder->port);
3503 	MISSING_CASE(encoder->port);
4310 		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
4450  * @encoder: encoder determining the type of port DPLL
4453  * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
4454  * DPLL selected will be based on the current mode of the encoder's port.