Lines Matching defs:dpll_hw_state

69 		       const struct intel_dpll_hw_state *dpll_hw_state);
86 struct intel_dpll_hw_state *dpll_hw_state);
94 const struct intel_dpll_hw_state *dpll_hw_state);
113 const struct intel_dpll_hw_state *dpll_hw_state);
357 const struct intel_dpll_hw_state *dpll_hw_state,
384 if (memcmp(dpll_hw_state,
386 sizeof(*dpll_hw_state)) == 0) {
435 const struct intel_dpll_hw_state *dpll_hw_state)
442 shared_dpll[pll->index].hw_state = *dpll_hw_state;
524 struct intel_dpll_hw_state *dpll_hw_state)
526 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
560 const struct intel_dpll_hw_state *dpll_hw_state)
562 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
625 &crtc_state->dpll_hw_state,
635 pll, &crtc_state->dpll_hw_state);
643 const struct intel_dpll_hw_state *dpll_hw_state)
645 const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
647 drm_printf(p, "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
690 const struct intel_dpll_hw_state *dpll_hw_state)
692 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
702 const struct intel_dpll_hw_state *dpll_hw_state)
704 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
745 struct intel_dpll_hw_state *dpll_hw_state)
747 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
767 struct intel_dpll_hw_state *dpll_hw_state)
769 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
994 const struct intel_dpll_hw_state *dpll_hw_state)
996 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
1040 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
1051 &crtc_state->dpll_hw_state);
1064 &crtc_state->dpll_hw_state,
1120 const struct intel_dpll_hw_state *dpll_hw_state)
1148 struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
1166 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
1172 const struct intel_dpll_hw_state *dpll_hw_state)
1174 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
1231 pll, &crtc_state->dpll_hw_state);
1249 const struct intel_dpll_hw_state *dpll_hw_state)
1251 const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
1253 drm_printf(p, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
1294 struct intel_dpll_hw_state *dpll_hw_state)
1376 const struct intel_dpll_hw_state *dpll_hw_state)
1378 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1398 const struct intel_dpll_hw_state *dpll_hw_state)
1400 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1423 struct intel_dpll_hw_state *dpll_hw_state)
1425 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1461 struct intel_dpll_hw_state *dpll_hw_state)
1463 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1734 const struct intel_dpll_hw_state *dpll_hw_state)
1736 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1807 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
1837 &crtc_state->dpll_hw_state);
1845 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
1882 const struct intel_dpll_hw_state *dpll_hw_state)
1884 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1940 &crtc_state->dpll_hw_state,
1944 &crtc_state->dpll_hw_state,
1952 pll, &crtc_state->dpll_hw_state);
1961 const struct intel_dpll_hw_state *dpll_hw_state)
1963 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1970 return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
1972 return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
1982 const struct intel_dpll_hw_state *dpll_hw_state)
1984 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
1986 drm_printf(p, "dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
2036 const struct intel_dpll_hw_state *dpll_hw_state)
2038 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2158 struct intel_dpll_hw_state *dpll_hw_state)
2160 struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2292 struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
2358 const struct intel_dpll_hw_state *dpll_hw_state)
2360 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2399 &crtc_state->dpll_hw_state);
2437 pll, &crtc_state->dpll_hw_state);
2452 const struct intel_dpll_hw_state *dpll_hw_state)
2454 const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
2456 drm_printf(p, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
2753 const struct intel_dpll_hw_state *dpll_hw_state)
2824 const struct intel_dpll_hw_state *dpll_hw_state)
2826 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
2886 struct intel_dpll_hw_state *dpll_hw_state)
2888 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
2992 struct intel_dpll_hw_state *dpll_hw_state)
2995 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3197 const struct intel_dpll_hw_state *dpll_hw_state)
3199 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3283 crtc_state->dpll_hw_state = port_dpll->hw_state;
3536 struct intel_dpll_hw_state *dpll_hw_state)
3538 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3603 struct intel_dpll_hw_state *dpll_hw_state)
3605 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3675 struct intel_dpll_hw_state *dpll_hw_state,
3678 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3736 struct intel_dpll_hw_state *dpll_hw_state)
3740 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
3745 struct intel_dpll_hw_state *dpll_hw_state)
3747 return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
3952 const struct intel_dpll_hw_state *dpll_hw_state)
3954 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3976 const struct intel_dpll_hw_state *dpll_hw_state)
3978 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
3997 const struct intel_dpll_hw_state *dpll_hw_state)
3999 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
4080 const struct intel_dpll_hw_state *dpll_hw_state)
4082 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
4084 drm_printf(p, "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, "
4473 * @dpll_hw_state: DPLL state from which to calculate the output frequency
4475 * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
4479 const struct intel_dpll_hw_state *dpll_hw_state)
4484 return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
4491 * @dpll_hw_state: DPLL's hardware state
4493 * Read out @pll's hardware state into @dpll_hw_state.
4497 struct intel_dpll_hw_state *dpll_hw_state)
4499 return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
4573 * @dpll_hw_state: hw state to be dumped
4575 * Dumo out the relevant values in @dpll_hw_state.
4579 const struct intel_dpll_hw_state *dpll_hw_state)
4582 i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
4587 ibx_dump_hw_state(p, dpll_hw_state);
4621 struct intel_dpll_hw_state dpll_hw_state = {};
4625 active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
4664 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4665 sizeof(dpll_hw_state)),