i915/display/intel_dpll.c

316 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
329 static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
331 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
334 int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
347 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
360 int chv_calc_dpll_params(int refclk, struct dpll *clock)
378 	if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
406 	hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe));
413 		hw_state->dpll &= ~(DPLL_LOCK_VLV |
425 	u32 dpll = hw_state->dpll;
427 	struct dpll clock;
431 	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
447 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
450 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
453 		switch (dpll & DPLL_MODE_MASK) {
455 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
459 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
465 				    "mode\n", (int)(dpll & DPLL_MODE_MASK));
481 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
489 			if (dpll & PLL_P1_DIVIDE_BY_TWO)
492 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
495 			if (dpll & PLL_P2_DIVIDE_BY_4)
520 	struct dpll clock;
524 	if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
547 	struct dpll clock;
552 	if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
580 			       const struct dpll *clock)
651 		    const struct dpll *match_clock,
652 		    struct dpll *best_clock)
655 	struct dpll clock;
709 		   const struct dpll *match_clock,
710 		   struct dpll *best_clock)
713 	struct dpll clock;
765 		   const struct dpll *match_clock,
766 		   struct dpll *best_clock)
769 	struct dpll clock;
816 			       const struct dpll *calculated_clock,
817 			       const struct dpll *best_clock,
859 		   const struct dpll *match_clock,
860 		   struct dpll *best_clock)
864 	struct dpll clock;
917 		   const struct dpll *match_clock,
918 		   struct dpll *best_clock)
923 	struct dpll clock;
973 			struct dpll *best_clock)
983 u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
985 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
988 static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
990 	return (1 << dpll->n) << 16 | dpll->m2;
999 		     const struct dpll *clock,
1000 		     const struct dpll *reduced_clock)
1004 	u32 dpll;
1006 	dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
1009 		dpll |= DPLLB_MODE_LVDS;
1011 		dpll |= DPLLB_MODE_DAC_SERIAL;
1015 		dpll |= (crtc_state->pixel_multiplier - 1)
1021 		dpll |= DPLL_SDVO_HIGH_SPEED;
1024 		dpll |= DPLL_SDVO_HIGH_SPEED;
1028 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1029 		dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1031 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
1034 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1040 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1043 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1046 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1049 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1055 		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1058 		dpll |= PLL_REF_INPUT_TVCLKINBC;
1061 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1063 		dpll |= PLL_REF_INPUT_DREFCLK;
1065 	return dpll;
1069 			      const struct dpll *clock,
1070 			      const struct dpll *reduced_clock)
1084 	hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);
1091 		     const struct dpll *clock,
1092 		     const struct dpll *reduced_clock)
1096 	u32 dpll;
1098 	dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;
1101 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1104 			dpll |= PLL_P1_DIVIDE_BY_TWO;
1106 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1108 			dpll |= PLL_P2_DIVIDE_BY_4;
1127 		dpll |= DPLL_DVO_2X_MODE;
1131 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1133 		dpll |= PLL_REF_INPUT_DREFCLK;
1135 	return dpll;
1139 			      const struct dpll *clock,
1140 			      const struct dpll *reduced_clock)
1147 	hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);
1250 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
1252 	return dpll->m < factor * dpll->n;
1255 static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)
1267 		    const struct dpll *clock,
1268 		    const struct dpll *reduced_clock)
1272 	u32 dpll;
1274 	dpll = DPLL_VCO_ENABLE;
1277 		dpll |= DPLLB_MODE_LVDS;
1279 		dpll |= DPLLB_MODE_DAC_SERIAL;
1281 	dpll |= (crtc_state->pixel_multiplier - 1)
1286 		dpll |= DPLL_SDVO_HIGH_SPEED;
1289 		dpll |= DPLL_SDVO_HIGH_SPEED;
1307 		dpll |= DPLL_SDVO_HIGH_SPEED;
1310 	dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1312 	dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1316 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1319 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1322 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1325 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1332 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1334 		dpll |= PLL_REF_INPUT_DREFCLK;
1336 	return dpll;
1340 			     const struct dpll *clock,
1341 			     const struct dpll *reduced_clock)
1349 	hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);
1391 				refclk, NULL, &crtc_state->dpll))
1394 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1396 	ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1397 			 &crtc_state->dpll);
1403 	crtc_state->port_clock = crtc_state->dpll.dot;
1425 	u32 dpll;
1427 	dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1431 		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1435 		dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
1437 	return dpll;
1444 	hw_state->dpll = vlv_dpll(crtc_state);
1451 	u32 dpll;
1453 	dpll = DPLL_SSC_REF_CLK_CHV |
1457 		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1461 		dpll |= DPLL_VCO_ENABLE;
1463 	return dpll;
1470 	hw_state->dpll = chv_dpll(crtc_state);
1484 				refclk, NULL, &crtc_state->dpll))
1487 	chv_calc_dpll_params(refclk, &crtc_state->dpll);
1495 	crtc_state->port_clock = crtc_state->dpll.dot;
1511 				refclk, NULL, &crtc_state->dpll))
1514 	vlv_calc_dpll_params(refclk, &crtc_state->dpll);
1522 	crtc_state->port_clock = crtc_state->dpll.dot;
1561 				refclk, NULL, &crtc_state->dpll))
1564 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1566 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1567 			  &crtc_state->dpll);
1569 	crtc_state->port_clock = crtc_state->dpll.dot;
1601 				refclk, NULL, &crtc_state->dpll))
1604 	pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1606 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1607 			  &crtc_state->dpll);
1609 	crtc_state->port_clock = crtc_state->dpll.dot;
1639 				 refclk, NULL, &crtc_state->dpll))
1642 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1644 	i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1645 			  &crtc_state->dpll);
1647 	crtc_state->port_clock = crtc_state->dpll.dot;
1681 				 refclk, NULL, &crtc_state->dpll))
1684 	i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1686 	i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1687 			  &crtc_state->dpll);
1689 	crtc_state->port_clock = crtc_state->dpll.dot;
1753 	ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
1777 	if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
1780 	ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
1794 		dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
1796 		dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
1798 		dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
1800 		dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
1802 		dev_priv->display.funcs.dpll = &chv_dpll_funcs;
1804 		dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
1806 		dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
1808 		dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
1810 		dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
1812 		dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
1845 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS);
1846 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1860 		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1865 		intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
1904 	const struct dpll *clock = &crtc_state->dpll;
1994 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
2016 		       hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
2018 	if (hw_state->dpll & DPLL_VCO_ENABLE) {
2031 	const struct dpll *clock = &crtc_state->dpll;
2141 	intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll);
2162 		       hw_state->dpll & ~DPLL_VCO_ENABLE);
2164 	if (hw_state->dpll & DPLL_VCO_ENABLE) {
2198  * @dpll: PLL configuration
2200  * Enable the PLL for @pipe using the supplied @dpll config. To be used
2205 		     const struct dpll *dpll)
2216 	crtc_state->dpll = *dpll;